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anv: add missing wokraround for texture cache invalidate

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Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18743>
This commit is contained in:
Lionel Landwerlin 2022-09-22 08:13:22 +03:00 • committed by Marge Bot
parent 8cb1deded6
commit f9dbb65e7f
1 changed files with 25 additions and 0 deletions
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25
src/intel/vulkan/genX_cmd_buffer.c
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@ -259,6 +259,18 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
pc.StateCacheInvalidationEnable = true;
#if GFX_VERx10 == 125
pc.InstructionCacheInvalidateEnable = true;
#endif
#if GFX_VER >= 9 && GFX_VER <= 11
/* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
*
* "Workaround : “CS Stall” bit in PIPE_CONTROL command must be
* always set for GPGPU workloads when “Texture Cache Invalidation
* Enable” bit is set".
*
* Workaround stopped appearing in TGL PRMs.
*/
pc.CommandStreamerStallEnable =
cmd_buffer->state.current_pipeline == GPGPU;
#endif
anv_debug_dump_pc(pc);
}
@ -2033,6 +2045,19 @@ genX(emit_apply_pipe_flushes)(struct anv_batch *batch,
pipe.InstructionCacheInvalidateEnable =
bits & ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT;
#if GFX_VER >= 9 && GFX_VER <= 11
/* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
*
* "Workaround : “CS Stall” bit in PIPE_CONTROL command must be
* always set for GPGPU workloads when “Texture Cache
* Invalidation Enable” bit is set".
*
* Workaround stopped appearing in TGL PRMs.
*/
if (current_pipeline == GPGPU && pipe.TextureCacheInvalidationEnable)
pipe.CommandStreamerStallEnable = true;
#endif
/* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
*
* "When VF Cache Invalidate is set “Post Sync Operation” must be