From f9dbb65e7feac3e5d8558e21b2a6a2928f3682b9 Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Thu, 22 Sep 2022 08:13:22 +0300 Subject: [PATCH] anv: add missing wokraround for texture cache invalidate Signed-off-by: Lionel Landwerlin Reviewed-by: Nanley Chery Cc: mesa-stable Part-of: --- src/intel/vulkan/genX_cmd_buffer.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 8d56a336c98..39f854db5be 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -259,6 +259,18 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer) pc.StateCacheInvalidationEnable = true; #if GFX_VERx10 == 125 pc.InstructionCacheInvalidateEnable = true; +#endif +#if GFX_VER >= 9 && GFX_VER <= 11 + /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL", + * + * "Workaround : “CS Stall” bit in PIPE_CONTROL command must be + * always set for GPGPU workloads when “Texture Cache Invalidation + * Enable” bit is set". + * + * Workaround stopped appearing in TGL PRMs. + */ + pc.CommandStreamerStallEnable = + cmd_buffer->state.current_pipeline == GPGPU; #endif anv_debug_dump_pc(pc); } @@ -2033,6 +2045,19 @@ genX(emit_apply_pipe_flushes)(struct anv_batch *batch, pipe.InstructionCacheInvalidateEnable = bits & ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT; +#if GFX_VER >= 9 && GFX_VER <= 11 + /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL", + * + * "Workaround : “CS Stall” bit in PIPE_CONTROL command must be + * always set for GPGPU workloads when “Texture Cache + * Invalidation Enable” bit is set". + * + * Workaround stopped appearing in TGL PRMs. + */ + if (current_pipeline == GPGPU && pipe.TextureCacheInvalidationEnable) + pipe.CommandStreamerStallEnable = true; +#endif + /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL", * * "When VF Cache Invalidate is set “Post Sync Operation” must be