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ac/info: add ac_fill_tiling_info

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Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40656>
This commit is contained in:
Pierre-Eric Pelloux-Prayer 2026-03-26 09:51:54 +01:00 • committed by Marge Bot
parent 79ebbf587e
commit f9c60f3699
2 changed files with 27 additions and 20 deletions
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46
src/amd/common/ac_gpu_info.c
View file

@ -399,6 +399,31 @@ ac_fill_compiler_info(struct radeon_info *info, struct drm_amdgpu_info_device *d
out->has_primid_instancing_bug = info->gfx_level == GFX6 && info->max_se == 1;
}
void
ac_fill_tiling_info(struct radeon_info *info, const struct amdgpu_gpu_info *amdinfo)
{
info->mc_arb_ramcfg = amdinfo->mc_arb_ramcfg;
info->gb_addr_config = amdinfo->gb_addr_cfg;
if (info->gfx_level >= GFX9) {
if (!info->has_graphics && info->family >= CHIP_GFX940)
info->gb_addr_config = 0;
info->num_tile_pipes = 1 << G_0098F8_NUM_PIPES(info->gb_addr_config);
assert((256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config)) ==
AMD_MEMCHANNEL_INTERLEAVE_BYTES);
} else {
unsigned pipe_config = G_009910_PIPE_CONFIG(amdinfo->gb_tile_mode[CIK_TILE_MODE_COLOR_2D]);
info->num_tile_pipes = ac_pipe_config_to_num_pipes(pipe_config);
assert((256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(info->gb_addr_config)) ==
AMD_MEMCHANNEL_INTERLEAVE_BYTES);
}
memcpy(info->si_tile_mode_array, amdinfo->gb_tile_mode, sizeof(amdinfo->gb_tile_mode));
memcpy(info->cik_macrotile_mode_array, amdinfo->gb_macro_tile_mode,
sizeof(amdinfo->gb_macro_tile_mode));
}
enum ac_query_gpu_info_result
ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
bool require_pci_bus_info)
@ -999,21 +1024,7 @@ ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
}
}
info->mc_arb_ramcfg = amdinfo.mc_arb_ramcfg;
info->gb_addr_config = amdinfo.gb_addr_cfg;
if (info->gfx_level >= GFX9) {
if (!info->has_graphics && info->family >= CHIP_GFX940)
info->gb_addr_config = 0;
info->num_tile_pipes = 1 << G_0098F8_NUM_PIPES(info->gb_addr_config);
assert((256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config)) ==
AMD_MEMCHANNEL_INTERLEAVE_BYTES);
} else {
unsigned pipe_config = G_009910_PIPE_CONFIG(amdinfo.gb_tile_mode[CIK_TILE_MODE_COLOR_2D]);
info->num_tile_pipes = ac_pipe_config_to_num_pipes(pipe_config);
assert((256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(info->gb_addr_config)) ==
AMD_MEMCHANNEL_INTERLEAVE_BYTES);
}
ac_fill_tiling_info(info, &amdinfo);
info->r600_has_virtual_memory = true;
/* LDS is 64KB per CU (4 SIMDs on GFX6-9, which is 16KB per SIMD).
@ -1281,11 +1292,6 @@ ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
info->min_good_cu_per_sa =
(info->num_cu / (info->num_se * info->max_sa_per_se * cu_group)) * cu_group;
memcpy(info->si_tile_mode_array, amdinfo.gb_tile_mode, sizeof(amdinfo.gb_tile_mode));
memcpy(info->cik_macrotile_mode_array, amdinfo.gb_macro_tile_mode,
sizeof(amdinfo.gb_macro_tile_mode));
info->pte_fragment_size = device_info.pte_fragment_size;
info->gart_page_size = device_info.gart_page_size;

1
src/amd/common/ac_gpu_info.h
View file

@ -487,6 +487,7 @@ enum ac_query_gpu_info_result {
enum ac_query_gpu_info_result ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
bool require_pci_bus_info);
void ac_fill_compiler_info(struct radeon_info *info, struct drm_amdgpu_info_device *device_info);
void ac_fill_tiling_info(struct radeon_info *info, const struct amdgpu_gpu_info *amdinfo);
void ac_compute_driver_uuid(char *uuid, size_t size);