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ac: remove ac_null_device

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Prefer AMDGPU shim.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40656>
This commit is contained in:
Pierre-Eric Pelloux-Prayer 2026-03-25 15:32:15 +01:00 • committed by Marge Bot
parent 42d4ec080c
commit 79ebbf587e
11 changed files with 48 additions and 219 deletions
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93
src/amd/common/ac_gpu_info.c
View file

@ -5,7 +5,6 @@
*/
#include "ac_gpu_info.h"
#include "ac_null_device.h"
#include "ac_shader_util.h"
#include "ac_debug.h"
#include "ac_surface.h"
@ -227,8 +226,11 @@ static bool handle_env_var_force_family(struct radeon_info *info)
{
const char *family = debug_get_option("AMD_FORCE_FAMILY", NULL);
if (family)
return ac_null_device_create(info, family);
if (family) {
/* Report AMD_FORCE_FAMILY as deprecated for one or two release cycles. */
fprintf(stderr, "AMD_FORCE_FAMILY=<family> has been removed. Please use AMDGPU drm-shim now.\n");
return false;
}
return true;
}
@ -632,8 +634,7 @@ ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
}
#define identify_chip(chipname) identify_chip2(chipname, chipname)
if (!info->family_overridden) {
switch (device_info.family) {
switch (device_info.family) {
case FAMILY_SI:
identify_chip(TAHITI);
identify_chip(PITCAIRN);
@ -720,45 +721,44 @@ ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
identify_chip(GFX1200);
identify_chip(GFX1201);
break;
}
if (info->family == CHIP_UNKNOWN) {
fprintf(stderr, "amdgpu: unknown (family_id, chip_external_rev): (%u, %u)\n",
device_info.family, device_info.external_rev);
return AC_QUERY_GPU_INFO_UNIMPLEMENTED_HW;
}
if (info->ip[AMD_IP_GFX].ver_major == 12 && info->ip[AMD_IP_GFX].ver_minor == 0)
info->gfx_level = GFX12;
else if (info->ip[AMD_IP_GFX].ver_major == 11 && info->ip[AMD_IP_GFX].ver_minor == 5)
info->gfx_level = GFX11_5;
else if (info->ip[AMD_IP_GFX].ver_major == 11 && info->ip[AMD_IP_GFX].ver_minor == 0)
info->gfx_level = GFX11;
else if (info->ip[AMD_IP_GFX].ver_major == 10 && info->ip[AMD_IP_GFX].ver_minor == 3)
info->gfx_level = GFX10_3;
else if (info->ip[AMD_IP_GFX].ver_major == 10 && info->ip[AMD_IP_GFX].ver_minor == 1)
info->gfx_level = GFX10;
else if (info->ip[AMD_IP_GFX].ver_major == 9 || info->ip[AMD_IP_COMPUTE].ver_major == 9)
info->gfx_level = GFX9;
else if (info->ip[AMD_IP_GFX].ver_major == 8)
info->gfx_level = GFX8;
else if (info->ip[AMD_IP_GFX].ver_major == 7)
info->gfx_level = GFX7;
else if (info->ip[AMD_IP_GFX].ver_major == 6)
info->gfx_level = GFX6;
else {
fprintf(stderr, "amdgpu: Unknown gfx version: %u.%u\n",
info->ip[AMD_IP_GFX].ver_major, info->ip[AMD_IP_GFX].ver_minor);
return AC_QUERY_GPU_INFO_UNIMPLEMENTED_HW;
}
info->family_id = device_info.family;
info->chip_external_rev = device_info.external_rev;
info->chip_rev = device_info.chip_rev;
const char *marketing_name = ac_drm_get_marketing_name(dev);
strncpy(info->marketing_name, marketing_name ? marketing_name : "AMD Unknown", sizeof(info->marketing_name));
}
if (info->family == CHIP_UNKNOWN) {
fprintf(stderr, "amdgpu: unknown (family_id, chip_external_rev): (%u, %u)\n",
device_info.family, device_info.external_rev);
return AC_QUERY_GPU_INFO_UNIMPLEMENTED_HW;
}
if (info->ip[AMD_IP_GFX].ver_major == 12 && info->ip[AMD_IP_GFX].ver_minor == 0)
info->gfx_level = GFX12;
else if (info->ip[AMD_IP_GFX].ver_major == 11 && info->ip[AMD_IP_GFX].ver_minor == 5)
info->gfx_level = GFX11_5;
else if (info->ip[AMD_IP_GFX].ver_major == 11 && info->ip[AMD_IP_GFX].ver_minor == 0)
info->gfx_level = GFX11;
else if (info->ip[AMD_IP_GFX].ver_major == 10 && info->ip[AMD_IP_GFX].ver_minor == 3)
info->gfx_level = GFX10_3;
else if (info->ip[AMD_IP_GFX].ver_major == 10 && info->ip[AMD_IP_GFX].ver_minor == 1)
info->gfx_level = GFX10;
else if (info->ip[AMD_IP_GFX].ver_major == 9 || info->ip[AMD_IP_COMPUTE].ver_major == 9)
info->gfx_level = GFX9;
else if (info->ip[AMD_IP_GFX].ver_major == 8)
info->gfx_level = GFX8;
else if (info->ip[AMD_IP_GFX].ver_major == 7)
info->gfx_level = GFX7;
else if (info->ip[AMD_IP_GFX].ver_major == 6)
info->gfx_level = GFX6;
else {
fprintf(stderr, "amdgpu: Unknown gfx version: %u.%u\n",
info->ip[AMD_IP_GFX].ver_major, info->ip[AMD_IP_GFX].ver_minor);
return AC_QUERY_GPU_INFO_UNIMPLEMENTED_HW;
}
info->family_id = device_info.family;
info->chip_external_rev = device_info.external_rev;
info->chip_rev = device_info.chip_rev;
const char *marketing_name = ac_drm_get_marketing_name(dev);
strncpy(info->marketing_name, marketing_name ? marketing_name : "AMD Unknown", sizeof(info->marketing_name));
#define VCN_IP_VERSION(mj, mn, rv) (((mj) << 16) | ((mn) << 8) | (rv))
for (unsigned i = AMD_IP_VCN_DEC; i <= AMD_IP_VCN_JPEG; ++i) {
@ -1000,8 +1000,7 @@ ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
}
info->mc_arb_ramcfg = amdinfo.mc_arb_ramcfg;
if (!info->family_overridden)
info->gb_addr_config = amdinfo.gb_addr_cfg;
info->gb_addr_config = amdinfo.gb_addr_cfg;
if (info->gfx_level >= GFX9) {
if (!info->has_graphics && info->family >= CHIP_GFX940)
info->gb_addr_config = 0;
@ -1282,8 +1281,7 @@ ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
info->min_good_cu_per_sa =
(info->num_cu / (info->num_se * info->max_sa_per_se * cu_group)) * cu_group;
if (!info->family_overridden)
memcpy(info->si_tile_mode_array, amdinfo.gb_tile_mode, sizeof(amdinfo.gb_tile_mode));
memcpy(info->si_tile_mode_array, amdinfo.gb_tile_mode, sizeof(amdinfo.gb_tile_mode));
memcpy(info->cik_macrotile_mode_array, amdinfo.gb_macro_tile_mode,
sizeof(amdinfo.gb_macro_tile_mode));
@ -1567,7 +1565,7 @@ ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
info->attribute_ring_size_per_se = 1400 * 1024;
num_prim_exports = 16368; /* also includes gs_alloc_req */
num_pos_exports = 16384;
} else if (info->l3_cache_size_mb || info->family_overridden) {
} else if (info->l3_cache_size_mb) {
info->attribute_ring_size_per_se = 1400 * 1024;
} else {
assert(info->num_se == 1);
@ -1805,7 +1803,6 @@ void ac_print_gpu_info(FILE *f, const struct radeon_info *info, int fd)
fprintf(f, " chip_rev = %i\n", info->chip_rev);
fprintf(f, "Flags:\n");
fprintf(f, " family_overridden = %u\n", info->family_overridden);
fprintf(f, " has_graphics = %i\n", info->has_graphics);
fprintf(f, " has_clear_state = %u\n", info->has_clear_state);
fprintf(f, " has_distributed_tess = %u\n", info->has_distributed_tess);

1
src/amd/common/ac_gpu_info.h
View file

@ -243,7 +243,6 @@ struct radeon_info {
uint32_t chip_rev; /* 0 = A0, 1 = A1, etc. */
/* Flags. */
bool family_overridden; /* AMD_FORCE_FAMILY was used, skip command submission */
bool has_graphics; /* false if the chip is compute-only */
bool has_clear_state;
bool has_distributed_tess;

82
src/amd/common/ac_null_device.c
View file

@ -1,82 +0,0 @@
/*
* Copyright © 2020 Valve Corporation
*
* SPDX-License-Identifier: MIT
*/
#include "ac_null_device.h"
#include "ac_gpu_info.h"
#include "util/u_string.h"
bool
ac_null_device_create(struct radeon_info *gpu_info, const char *family)
{
unsigned i;
gpu_info->gfx_level = CLASS_UNKNOWN;
gpu_info->family = CHIP_UNKNOWN;
strcpy(gpu_info->marketing_name, "AMD Unknown");
for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
if (!strcasecmp(family, ac_get_family_name(i))) {
/* Override family and gfx_level. */
gpu_info->family = i;
if (gpu_info->family >= CHIP_GFX1200)
gpu_info->gfx_level = GFX12;
else if (gpu_info->family >= CHIP_NAVI31)
gpu_info->gfx_level = GFX11;
else if (i >= CHIP_NAVI21)
gpu_info->gfx_level = GFX10_3;
else if (i >= CHIP_NAVI10)
gpu_info->gfx_level = GFX10;
else if (i >= CHIP_VEGA10)
gpu_info->gfx_level = GFX9;
else if (i >= CHIP_TONGA)
gpu_info->gfx_level = GFX8;
else if (i >= CHIP_BONAIRE)
gpu_info->gfx_level = GFX7;
else
gpu_info->gfx_level = GFX6;
}
}
if (gpu_info->family == CHIP_UNKNOWN)
return false;
gpu_info->pci_id = pci_ids[gpu_info->family].pci_id;
gpu_info->max_se = pci_ids[gpu_info->family].has_dedicated_vram ? 4 : 1;
gpu_info->num_se = gpu_info->max_se;
gpu_info->has_timeline_syncobj = true;
gpu_info->has_vm_always_valid = true;
gpu_info->has_image_opcodes = true;
gpu_info->lds_size_per_workgroup = gpu_info->gfx_level >= GFX7 ? 64 * 1024 : 32 * 1024;
gpu_info->max_render_backends = pci_ids[gpu_info->family].num_render_backends;
gpu_info->has_dedicated_vram = pci_ids[gpu_info->family].has_dedicated_vram;
gpu_info->has_distributed_tess =
gpu_info->gfx_level >= GFX10 || (gpu_info->gfx_level >= GFX8 && gpu_info->max_se >= 2);
gpu_info->address32_hi = gpu_info->gfx_level >= GFX9 ? 0xffff8000u : 0x0;
gpu_info->has_rbplus = gpu_info->family == CHIP_STONEY || gpu_info->gfx_level >= GFX9;
gpu_info->rbplus_allowed =
gpu_info->has_rbplus &&
(gpu_info->family == CHIP_STONEY || gpu_info->family == CHIP_VEGA12 || gpu_info->family == CHIP_RAVEN ||
gpu_info->family == CHIP_RAVEN2 || gpu_info->family == CHIP_RENOIR || gpu_info->gfx_level >= GFX10_3);
gpu_info->mesh_fast_launch_2 = gpu_info->gfx_level >= GFX11;
gpu_info->hs_offchip_workgroup_dw_size = gpu_info->family == CHIP_HAWAII ? 4096 : 8192;
gpu_info->has_graphics = true;
gpu_info->ip[AMD_IP_GFX].num_queues = 1;
gpu_info->gart_page_size = 4096;
ac_fill_compiler_info(gpu_info, NULL);
gpu_info->family_overridden = true;
return true;
}

59
src/amd/common/ac_null_device.h
View file

@ -1,59 +0,0 @@
/*
* Copyright © 2025 Valve Corporation
*
* SPDX-License-Identifier: MIT
*/
#ifndef RADV_NULL_DEVICE_H
#define RADV_NULL_DEVICE_H
#include <stdbool.h>
#include <stdint.h>
#include "amd_family.h"
/* Hardcode some GPU info that are needed for the driver or for some tools. */
static const struct {
uint32_t pci_id;
uint32_t num_render_backends;
bool has_dedicated_vram;
} pci_ids[] = {
/* clang-format off */
[CHIP_TAHITI] = {0x6780, 8, true},
[CHIP_PITCAIRN] = {0x6800, 8, true},
[CHIP_VERDE] = {0x6820, 4, true},
[CHIP_OLAND] = {0x6060, 2, true},
[CHIP_HAINAN] = {0x6660, 2, true},
[CHIP_BONAIRE] = {0x6640, 4, true},
[CHIP_KAVERI] = {0x1304, 2, false},
[CHIP_KABINI] = {0x9830, 2, false},
[CHIP_HAWAII] = {0x67A0, 16, true},
[CHIP_TONGA] = {0x6920, 8, true},
[CHIP_ICELAND] = {0x6900, 2, true},
[CHIP_CARRIZO] = {0x9870, 2, false},
[CHIP_FIJI] = {0x7300, 16, true},
[CHIP_STONEY] = {0x98E4, 2, false},
[CHIP_POLARIS10] = {0x67C0, 8, true},
[CHIP_POLARIS11] = {0x67E0, 4, true},
[CHIP_POLARIS12] = {0x6980, 4, true},
[CHIP_VEGAM] = {0x694C, 4, true},
[CHIP_VEGA10] = {0x6860, 16, true},
[CHIP_VEGA12] = {0x69A0, 8, true},
[CHIP_VEGA20] = {0x66A0, 16, true},
[CHIP_RAVEN] = {0x15DD, 2, false},
[CHIP_RENOIR] = {0x1636, 2, false},
[CHIP_MI100] = {0x738C, 2, true},
[CHIP_NAVI10] = {0x7310, 16, true},
[CHIP_NAVI12] = {0x7360, 8, true},
[CHIP_NAVI14] = {0x7340, 8, true},
[CHIP_NAVI21] = {0x73A0, 16, true},
[CHIP_VANGOGH] = {0x163F, 8, false},
[CHIP_NAVI22] = {0x73C0, 8, true},
[CHIP_NAVI23] = {0x73E0, 8, true},
[CHIP_NAVI31] = {0x744C, 24, true},
[CHIP_GFX1201] = {0x7550, 16, true},
/* clang-format on */
};
bool ac_null_device_create(struct radeon_info *gpu_info, const char *family);
#endif /* RADV_NULL_DEVICE_H */

11
src/amd/common/ac_surface.c
View file

@ -4198,12 +4198,10 @@ void ac_surface_compute_umd_metadata(const struct radeon_info *info, const struc
*/
/* metadata image format version */
metadata[0] = (include_tool_md || info->family_overridden) ? 3 : 1;
metadata[0] = include_tool_md ? 3 : 1;
if (include_tool_md)
metadata[0] |= 1u << (16 + AC_SURF_METADATA_FLAG_EXTRA_MD_BIT);
if (info->family_overridden)
metadata[0] |= 1u << (16 + AC_SURF_METADATA_FLAG_FAMILY_OVERRIDEN_BIT);
/* Tiling modes are ambiguous without a PCI ID. */
metadata[1] = ac_get_umd_metadata_word1(info);
@ -4240,13 +4238,6 @@ void ac_surface_compute_umd_metadata(const struct radeon_info *info, const struc
*size_metadata = 11 * 4;
}
}
if (info->family_overridden) {
int n_dw = *size_metadata / 4;
assert(n_dw < 64 - 1);
metadata[n_dw] = info->gfx_level;
*size_metadata += 4;
}
}
static uint32_t ac_surface_get_pitch_align(const struct radeon_info *info,

2
src/amd/common/meson.build
View file

@ -120,8 +120,6 @@ amd_common_files = files(
'ac_formats.c',
'ac_formats.h',
'ac_linux_drm.h',
'ac_null_device.c',
'ac_null_device.h',
'ac_shadowed_regs.c',
'ac_shadowed_regs.h',
'ac_spm.c',

6
src/amd/vulkan/radv_device.c
View file

@ -1248,12 +1248,6 @@ radv_CreateDevice(VkPhysicalDevice physicalDevice, const VkDeviceCreateInfo *pCr
/* PKT3_LOAD_SH_REG_INDEX is supported on GFX8+, but it hangs with compute queues until GFX10.3. */
device->load_grid_size_from_user_sgpr = pdev->info.gfx_level >= GFX10_3;
/* If this is a NULL device, we are done here. */
if (pdev->info.family_overridden) {
*pDevice = radv_device_to_handle(device);
return VK_SUCCESS;
}
device->ws = pdev->ws;
device->vk.sync = device->ws->get_sync_provider(device->ws);

1
src/amd/vulkan/radv_physical_device.c
View file

@ -20,7 +20,6 @@
#include "vk_log.h"
#include "vk_shader_module.h"
#include "common/ac_null_device.h"
#include "util/disk_cache.h"
#include "util/hex.h"
#include "util/u_debug.h"

8
src/amd/vulkan/radv_shader.c
View file

@ -2997,11 +2997,6 @@ radv_shader_create_uncached(struct radv_device *device, const struct radv_shader
}
}
if (radv_device_physical(device)->info.family_overridden) {
*out_shader = shader;
return VK_SUCCESS;
}
if (replay_block) {
shader->alloc = radv_replay_shader_arena_block(device, replay_block, shader);
if (!shader->alloc) {
@ -3107,9 +3102,6 @@ radv_shader_part_create(struct radv_device *device, struct radv_shader_part_bina
shader_part->cb_shader_mask = binary->info.cb_shader_mask;
shader_part->spi_shader_z_format = binary->info.spi_shader_z_format;
if (radv_device_physical(device)->info.family_overridden)
return shader_part;
/* Allocate memory and upload. */
shader_part->alloc = radv_alloc_shader_memory(device, shader_part->code_size, false, NULL);
if (!shader_part->alloc)

2
src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
View file

@ -663,7 +663,7 @@ static struct amdgpu_winsys_bo *amdgpu_create_bo(struct amdgpu_winsys *aws,
}
}
if (flags & RADEON_FLAG_GFX12_ALLOW_DCC && !aws->info.family_overridden)
if (flags & RADEON_FLAG_GFX12_ALLOW_DCC)
request.flags |= AMDGPU_GEM_CREATE_GFX12_DCC;
/* Set AMDGPU_GEM_CREATE_VIRTIO_SHARED if the driver didn't disable buffer sharing. */

2
src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
View file

@ -57,7 +57,7 @@ static bool do_winsys_init(struct amdgpu_winsys *aws,
aws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL ||
strstr(debug_get_option("AMD_DEBUG", ""), "check_vm") != NULL;
aws->noop_cs = aws->info.family_overridden || debug_get_bool_option("RADEON_NOOP", false);
aws->noop_cs = debug_get_bool_option("RADEON_NOOP", false);
#if MESA_DEBUG
aws->debug_all_bos = debug_get_option_all_bos();
#endif