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freedreno: c++-proofing

Browse source 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21846>
This commit is contained in:
Rob Clark 2022-07-17 11:04:54 -07:00 • committed by Marge Bot
parent 05958fa6c9
commit f921b7c09b
49 changed files with 241 additions and 101 deletions
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6
src/freedreno/fdl/fd6_format_table.h
View file

@ -31,10 +31,14 @@
#include "util/format/u_format.h"
#include "util/u_math.h"
#include "common/freedreno_common.h"
#include "adreno_pm4.xml.h"
#include "adreno_common.xml.h"
#include "a6xx.xml.h"
BEGINC;
static inline enum a6xx_tex_swiz
fdl6_swiz(unsigned char swiz)
{
@ -60,4 +64,6 @@ enum a6xx_format fd6_color_format(enum pipe_format format,
enum a3xx_color_swap fd6_color_swap(enum pipe_format format,
enum a6xx_tile_mode tile_mode) ATTRIBUTE_CONST;
ENDC;
#endif /* FD6_FORMAT_TABLE_H */

6
src/freedreno/fdl/freedreno_layout.h
View file

@ -31,6 +31,10 @@
#include "util/u_debug.h"
#include "util/u_math.h"
#include "common/freedreno_common.h"
BEGINC;
/* Shared freedreno mipmap layout helper
*
* It does *not* attempt to track surface transitions, in particular
@ -330,4 +334,6 @@ void
fdl6_format_swiz(enum pipe_format format, bool has_z24uint_s8uint,
unsigned char *format_swiz);
ENDC;
#endif /* FREEDRENO_LAYOUT_H_ */

2
src/freedreno/vulkan/meson.build
View file

@ -78,6 +78,8 @@ if freedreno_kmds.contains('msm')
tu_deps += dep_libdrm
endif
tu_flags += '-Wno-array-bounds'
tu_tracepoints = custom_target(
'tu_tracepoints.[ch]',
input: 'tu_tracepoints.py',

14
src/gallium/drivers/freedreno/a6xx/fd6_blend.c
View file

@ -54,7 +54,7 @@ blend_func(unsigned func)
return BLEND_DST_MINUS_SRC;
default:
DBG("invalid blend func: %x", func);
return 0;
return (enum a3xx_rb_blend_opcode)0;
}
}
@ -69,11 +69,11 @@ __fd6_setup_blend_variant(struct fd6_blend_stateobj *blend,
unsigned mrt_blend = 0;
if (cso->logicop_enable) {
rop = cso->logicop_func; /* maps 1:1 */
reads_dest = util_logicop_reads_dest(cso->logicop_func);
rop = (enum a3xx_rop_code)cso->logicop_func; /* maps 1:1 */
reads_dest = util_logicop_reads_dest((enum pipe_logicop)cso->logicop_func);
}
so = rzalloc_size(blend, sizeof(*so));
so = (struct fd6_blend_variant *)rzalloc_size(blend, sizeof(*so));
if (!so)
return NULL;
@ -153,7 +153,7 @@ fd6_blend_state_create(struct pipe_context *pctx,
{
struct fd6_blend_stateobj *so;
so = rzalloc_size(NULL, sizeof(*so));
so = (struct fd6_blend_stateobj *)rzalloc_size(NULL, sizeof(*so));
if (!so)
return NULL;
@ -161,7 +161,7 @@ fd6_blend_state_create(struct pipe_context *pctx,
so->ctx = fd_context(pctx);
if (cso->logicop_enable) {
so->reads_dest |= util_logicop_reads_dest(cso->logicop_func);
so->reads_dest |= util_logicop_reads_dest((enum pipe_logicop)cso->logicop_func);
}
so->use_dual_src_blend =
@ -187,7 +187,7 @@ fd6_blend_state_create(struct pipe_context *pctx,
void
fd6_blend_state_delete(struct pipe_context *pctx, void *hwcso)
{
struct fd6_blend_stateobj *so = hwcso;
struct fd6_blend_stateobj *so = (struct fd6_blend_stateobj *)hwcso;
util_dynarray_foreach (&so->variants, struct fd6_blend_variant *, vp) {
struct fd6_blend_variant *v = *vp;

4
src/gallium/drivers/freedreno/a6xx/fd6_blend.h
View file

@ -34,6 +34,8 @@
#include "freedreno_context.h"
#include "freedreno_util.h"
BEGINC;
/**
* Since the sample-mask is part of the hw blend state, we need to have state
* variants per sample-mask value. But we don't expect the sample-mask state
@ -90,4 +92,6 @@ void *fd6_blend_state_create(struct pipe_context *pctx,
const struct pipe_blend_state *cso);
void fd6_blend_state_delete(struct pipe_context *, void *hwcso);
ENDC;
#endif /* FD6_BLEND_H_ */

19
src/gallium/drivers/freedreno/a6xx/fd6_blitter.c
View file

@ -107,7 +107,7 @@ fd6_ifmt(enum a6xx_format fmt)
default:
unreachable("bad format");
return 0;
return (enum a6xx_2d_ifmt)0;
}
}
@ -547,9 +547,12 @@ emit_blit_dst(struct fd_ringbuffer *ring, struct pipe_resource *prsc,
enum pipe_format pfmt, unsigned level, unsigned layer)
{
struct fd_resource *dst = fd_resource(prsc);
enum a6xx_format fmt = fd6_color_format(pfmt, dst->layout.tile_mode);
enum a6xx_tile_mode tile = fd_resource_tile_mode(prsc, level);
enum a3xx_color_swap swap = fd6_color_swap(pfmt, dst->layout.tile_mode);
enum a6xx_format fmt =
fd6_color_format(pfmt, (enum a6xx_tile_mode)dst->layout.tile_mode);
enum a6xx_tile_mode tile =
(enum a6xx_tile_mode)fd_resource_tile_mode(prsc, level);
enum a3xx_color_swap swap =
fd6_color_swap(pfmt, (enum a6xx_tile_mode)dst->layout.tile_mode);
uint32_t pitch = fd_resource_pitch(dst, level);
bool ubwc_enabled = fd_resource_ubwc_enabled(dst, level);
unsigned off = fd_resource_offset(dst, level, layer);
@ -586,10 +589,12 @@ emit_blit_src(struct fd_ringbuffer *ring, const struct pipe_blit_info *info,
unsigned layer, unsigned nr_samples, bool sample_0)
{
struct fd_resource *src = fd_resource(info->src.resource);
enum a6xx_format sfmt = fd6_texture_format(info->src.format, src->layout.tile_mode);
enum a6xx_format sfmt =
fd6_texture_format(info->src.format, (enum a6xx_tile_mode)src->layout.tile_mode);
enum a6xx_tile_mode stile =
fd_resource_tile_mode(info->src.resource, info->src.level);
enum a3xx_color_swap sswap = fd6_texture_swap(info->src.format, src->layout.tile_mode);
(enum a6xx_tile_mode)fd_resource_tile_mode(info->src.resource, info->src.level);
enum a3xx_color_swap sswap =
fd6_texture_swap(info->src.format, (enum a6xx_tile_mode)src->layout.tile_mode);
uint32_t pitch = fd_resource_pitch(src, info->src.level);
bool subwc_enabled = fd_resource_ubwc_enabled(src, info->src.level);
unsigned soff = fd_resource_offset(src, info->src.level, layer);

4
src/gallium/drivers/freedreno/a6xx/fd6_blitter.h
View file

@ -32,6 +32,8 @@
#include "freedreno_context.h"
BEGINC;
void fd6_blitter_init(struct pipe_context *pctx);
unsigned fd6_tile_mode(const struct pipe_resource *tmpl);
@ -46,4 +48,6 @@ void fd6_clear_surface(struct fd_context *ctx, struct fd_ringbuffer *ring,
void fd6_resolve_tile(struct fd_batch *batch, struct fd_ringbuffer *ring,
uint32_t base, struct pipe_surface *psurf, uint32_t unknown_8c01) assert_dt;
ENDC;
#endif /* FD6_BLIT_H_ */

10
src/gallium/drivers/freedreno/a6xx/fd6_compute.c
View file

@ -106,14 +106,15 @@ cs_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
static void
fd6_launch_grid(struct fd_context *ctx, const struct pipe_grid_info *info) in_dt
{
struct fd6_compute_state *cs = ctx->compute;
struct fd6_compute_state *cs = (struct fd6_compute_state *)ctx->compute;
struct fd_ringbuffer *ring = ctx->batch->draw;
unsigned nglobal = 0;
if (unlikely(!cs->v)) {
struct ir3_shader_state *hwcso = (struct ir3_shader_state *)cs->hwcso;
struct ir3_shader_key key = {};
cs->v = ir3_shader_variant(ir3_get_shader(cs->hwcso), key, false, &ctx->debug);
cs->v = ir3_shader_variant(ir3_get_shader(hwcso), key, false, &ctx->debug);
if (!cs->v)
return;
@ -246,7 +247,8 @@ static void *
fd6_compute_state_create(struct pipe_context *pctx,
const struct pipe_compute_state *cso)
{
struct fd6_compute_state *hwcso = calloc(1, sizeof(*hwcso));
struct fd6_compute_state *hwcso =
(struct fd6_compute_state *)calloc(1, sizeof(*hwcso));
hwcso->hwcso = ir3_shader_compute_state_create(pctx, cso);
return hwcso;
}
@ -254,7 +256,7 @@ fd6_compute_state_create(struct pipe_context *pctx,
static void
fd6_compute_state_delete(struct pipe_context *pctx, void *_hwcso)
{
struct fd6_compute_state *hwcso = _hwcso;
struct fd6_compute_state *hwcso = (struct fd6_compute_state *)_hwcso;
ir3_shader_state_delete(pctx, hwcso->hwcso);
if (hwcso->stateobj)
fd_ringbuffer_del(hwcso->stateobj);

1
src/gallium/drivers/freedreno/a6xx/fd6_compute.h
View file

@ -36,6 +36,7 @@ struct fd6_compute_state {
uint32_t user_consts_cmdstream_size;
};
EXTERNC
void fd6_compute_init(struct pipe_context *pctx);
#endif /* FD6_COMPUTE_H_ */

4
src/gallium/drivers/freedreno/a6xx/fd6_const.h
View file

@ -27,6 +27,8 @@
#include "fd6_emit.h"
BEGINC;
struct fd_ringbuffer *fd6_build_tess_consts(struct fd6_emit *emit) assert_dt;
unsigned fd6_user_consts_cmdstream_size(struct ir3_shader_variant *v);
struct fd_ringbuffer *fd6_build_user_consts(struct fd6_emit *emit) assert_dt;
@ -48,4 +50,6 @@ void fd6_emit_link_map(struct fd_screen *screen,
const struct ir3_shader_variant *v,
struct fd_ringbuffer *ring) assert_dt;
ENDC;
#endif /* FD6_CONST_H */

4
src/gallium/drivers/freedreno/a6xx/fd6_context.c
View file

@ -89,7 +89,7 @@ fd6_vertex_state_create(struct pipe_context *pctx, unsigned num_elements,
OUT_PKT4(ring, REG_A6XX_VFD_DECODE(0), 2 * num_elements);
for (int32_t i = 0; i < num_elements; i++) {
const struct pipe_vertex_element *elem = &elements[i];
enum pipe_format pfmt = elem->src_format;
enum pipe_format pfmt = (enum pipe_format)elem->src_format;
enum a6xx_format fmt = fd6_vertex_format(pfmt);
bool isint = util_format_is_pure_integer(pfmt);
assert(fmt != FMT6_NONE);
@ -112,7 +112,7 @@ fd6_vertex_state_create(struct pipe_context *pctx, unsigned num_elements,
static void
fd6_vertex_state_delete(struct pipe_context *pctx, void *hwcso)
{
struct fd6_vertex_stateobj *so = hwcso;
struct fd6_vertex_stateobj *so = (struct fd6_vertex_stateobj *)hwcso;
fd_ringbuffer_del(so->stateobj);
FREE(hwcso);

4
src/gallium/drivers/freedreno/a6xx/fd6_context.h
View file

@ -38,6 +38,8 @@
#include "a6xx.xml.h"
BEGINC;
struct fd6_lrz_state {
union {
struct {
@ -195,4 +197,6 @@ fd6_vertex_stateobj(void *p)
return (struct fd6_vertex_stateobj *)p;
}
ENDC;
#endif /* FD6_CONTEXT_H_ */

41
src/gallium/drivers/freedreno/a6xx/fd6_draw.c
View file

@ -138,24 +138,27 @@ get_program_state(struct fd_context *ctx, const struct pipe_draw_info *info)
{
struct fd6_context *fd6_ctx = fd6_context(ctx);
struct ir3_cache_key key = {
.vs = ctx->prog.vs,
.gs = ctx->prog.gs,
.fs = ctx->prog.fs,
.key = {
.rasterflat = ctx->rasterizer->flatshade,
.ucp_enables = ctx->rasterizer->clip_plane_enable,
.sample_shading = (ctx->min_samples > 1),
.msaa = (ctx->framebuffer.samples > 1),
},
.vs = (struct ir3_shader_state *)ctx->prog.vs,
.gs = (struct ir3_shader_state *)ctx->prog.gs,
.fs = (struct ir3_shader_state *)ctx->prog.fs,
.clip_plane_enable = ctx->rasterizer->clip_plane_enable,
.patch_vertices = ctx->patch_vertices,
};
if (info->mode == PIPE_PRIM_PATCHES) {
struct shader_info *gs_info = ir3_get_shader_info(ctx->prog.gs);
/* Some gcc versions get confused about designated order, so workaround
* by not initializing these inline:
*/
key.key.ucp_enables = ctx->rasterizer->clip_plane_enable;
key.key.sample_shading = (ctx->min_samples > 1);
key.key.msaa = (ctx->framebuffer.samples > 1);
key.key.rasterflat = ctx->rasterizer->flatshade;
key.hs = ctx->prog.hs;
key.ds = ctx->prog.ds;
if (info->mode == PIPE_PRIM_PATCHES) {
struct shader_info *gs_info =
ir3_get_shader_info((struct ir3_shader_state *)ctx->prog.gs);
key.hs = (struct ir3_shader_state *)ctx->prog.hs;
key.ds = (struct ir3_shader_state *)ctx->prog.ds;
struct shader_info *ds_info = ir3_get_shader_info(key.ds);
key.key.tessellation = ir3_tess_mode(ds_info->tess._primitive_mode);
@ -193,7 +196,8 @@ flush_streamout(struct fd_context *ctx, struct fd6_emit *emit)
for (unsigned i = 0; i < PIPE_MAX_SO_BUFFERS; i++) {
if (emit->streamout_mask & (1 << i)) {
fd6_event_write(ctx->batch, ring, FLUSH_SO_0 + i, false);
enum vgt_event_type evt = (enum vgt_event_type)(FLUSH_SO_0 + i);
fd6_event_write(ctx->batch, ring, evt, false);
}
}
}
@ -292,7 +296,8 @@ fd6_draw_vbos(struct fd_context *ctx, const struct pipe_draw_info *info,
}
if (info->mode == PIPE_PRIM_PATCHES) {
struct shader_info *ds_info = ir3_get_shader_info(ctx->prog.ds);
struct shader_info *ds_info =
ir3_get_shader_info((struct ir3_shader_state *)ctx->prog.ds);
unsigned tessellation = ir3_tess_mode(ds_info->tess._primitive_mode);
uint32_t factor_stride = ir3_tess_factor_stride(tessellation);
@ -300,9 +305,9 @@ fd6_draw_vbos(struct fd_context *ctx, const struct pipe_draw_info *info,
STATIC_ASSERT(IR3_TESS_ISOLINES == TESS_ISOLINES + 1);
STATIC_ASSERT(IR3_TESS_TRIANGLES == TESS_TRIANGLES + 1);
STATIC_ASSERT(IR3_TESS_QUADS == TESS_QUADS + 1);
draw0.patch_type = tessellation - 1;
draw0.patch_type = (enum a6xx_patch_type)(tessellation - 1);
draw0.prim_type = DI_PT_PATCHES0 + ctx->patch_vertices;
draw0.prim_type = (enum pc_di_primtype)(DI_PT_PATCHES0 + ctx->patch_vertices);
draw0.tess_enable = true;
/* maximum number of patches that can fit in tess factor/param buffers */
@ -501,7 +506,7 @@ fd6_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth) a
OUT_RING(ring, A6XX_GRAS_2D_DST_BR_X(zsbuf->lrz_width - 1) |
A6XX_GRAS_2D_DST_BR_Y(zsbuf->lrz_height - 1));
fd6_event_write(batch, ring, 0x3f, false);
fd6_event_write(batch, ring, (enum vgt_event_type)0x3f, false);
if (screen->info->a6xx.magic.RB_DBG_ECO_CNTL_blit != screen->info->a6xx.magic.RB_DBG_ECO_CNTL) {
/* This a non-context register, so we have to WFI before changing. */

1
src/gallium/drivers/freedreno/a6xx/fd6_draw.h
View file

@ -34,6 +34,7 @@
#include "fd6_context.h"
EXTERNC
void fd6_draw_init(struct pipe_context *pctx);
#endif /* FD6_DRAW_H_ */

6
src/gallium/drivers/freedreno/a6xx/fd6_emit.c
View file

@ -530,7 +530,7 @@ build_prim_mode(struct fd6_emit *emit, struct fd_context *ctx, bool gmem)
prim_mode = NO_FLUSH;
}
OUT_REG(ring, A6XX_GRAS_SC_CNTL(.ccusinglecachelinesize = 2,
.single_prim_mode = prim_mode));
.single_prim_mode = (enum a6xx_single_prim_mode)prim_mode));
return ring;
}
@ -553,7 +553,7 @@ fd6_emit_3d_state(struct fd_ringbuffer *ring, struct fd6_emit *emit)
}
u_foreach_bit (b, emit->dirty_groups) {
enum fd6_state_id group = b;
enum fd6_state_id group = (enum fd6_state_id)b;
struct fd_ringbuffer *state = NULL;
switch (group) {
@ -706,7 +706,7 @@ fd6_emit_cs_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
(BIT(FD6_GROUP_PROG) | BIT(FD6_GROUP_CS_TEX) | BIT(FD6_GROUP_CS_BINDLESS));
u_foreach_bit (b, gen_dirty) {
enum fd6_state_id group = b;
enum fd6_state_id group = (enum fd6_state_id)b;
switch (group) {
case FD6_GROUP_PROG:

6
src/gallium/drivers/freedreno/a6xx/fd6_emit.h
View file

@ -306,7 +306,7 @@ fd6_stage2shadersb(gl_shader_stage type)
return SB6_CS_SHADER;
default:
unreachable("bad shader type");
return ~0;
return (enum a6xx_state_block)~0;
}
}
@ -326,6 +326,8 @@ fd6_gl2spacing(enum gl_tess_spacing spacing)
}
}
BEGINC;
void fd6_emit_3d_state(struct fd_ringbuffer *ring,
struct fd6_emit *emit) assert_dt;
@ -337,6 +339,8 @@ void fd6_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring);
void fd6_emit_init_screen(struct pipe_screen *pscreen);
ENDC;
static inline void
fd6_emit_ib(struct fd_ringbuffer *ring, struct fd_ringbuffer *target)
{

19
src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
View file

@ -85,7 +85,7 @@ emit_mrt(struct fd_ringbuffer *ring, struct pipe_framebuffer_state *pfb,
* the effects of the fragment on the framebuffer contents are undefined."
*/
unsigned max_layer_index = 0;
enum a6xx_format mrt0_format = 0;
enum a6xx_format mrt0_format = (enum a6xx_format)0;
for (i = 0; i < pfb->nr_cbufs; i++) {
enum a3xx_color_swap swap = WZYX;
@ -105,7 +105,8 @@ emit_mrt(struct fd_ringbuffer *ring, struct pipe_framebuffer_state *pfb,
uint32_t base = gmem ? gmem->cbuf_base[i] : 0;
slice = fd_resource_slice(rsc, psurf->u.tex.level);
uint32_t tile_mode = fd_resource_tile_mode(psurf->texture, psurf->u.tex.level);
enum a6xx_tile_mode tile_mode = (enum a6xx_tile_mode)
fd_resource_tile_mode(psurf->texture, psurf->u.tex.level);
enum a6xx_format format = fd6_color_format(pformat, tile_mode);
sint = util_format_is_pure_sint(pformat);
uint = util_format_is_pure_uint(pformat);
@ -118,7 +119,7 @@ emit_mrt(struct fd_ringbuffer *ring, struct pipe_framebuffer_state *pfb,
stride = fd_resource_pitch(rsc, psurf->u.tex.level);
array_stride = fd_resource_layer_stride(rsc, psurf->u.tex.level);
swap = fd6_color_swap(pformat, rsc->layout.tile_mode);
swap = fd6_color_swap(pformat, (enum a6xx_tile_mode)rsc->layout.tile_mode);
max_layer_index = psurf->u.tex.last_layer - psurf->u.tex.first_layer;
@ -274,7 +275,8 @@ patch_fb_read_gmem(struct fd_batch *batch)
/* always TILE6_2 mode in GMEM, which also means no swap: */
uint32_t descriptor[FDL6_TEX_CONST_DWORDS] = {
A6XX_TEX_CONST_0_FMT(fd6_texture_format(format, rsc->layout.tile_mode)) |
A6XX_TEX_CONST_0_FMT(fd6_texture_format(
format, (enum a6xx_tile_mode)rsc->layout.tile_mode)) |
A6XX_TEX_CONST_0_SAMPLES(fd_msaa_samples(prsc->nr_samples)) |
A6XX_TEX_CONST_0_SWAP(WZYX) |
A6XX_TEX_CONST_0_TILE_MODE(TILE6_2) |
@ -528,7 +530,8 @@ static void
check_vsc_overflow(struct fd_context *ctx)
{
struct fd6_context *fd6_ctx = fd6_context(ctx);
struct fd6_control *control = fd_bo_map(fd6_ctx->control_mem);
struct fd6_control *control =
(struct fd6_control *)fd_bo_map(fd6_ctx->control_mem);
uint32_t vsc_overflow = control->vsc_overflow;
if (!vsc_overflow)
@ -1013,11 +1016,13 @@ emit_blit(struct fd_batch *batch, struct fd_ringbuffer *ring, uint32_t base,
assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
uint32_t tile_mode = fd_resource_tile_mode(&rsc->b.b, psurf->u.tex.level);
enum a6xx_tile_mode tile_mode = (enum a6xx_tile_mode)
fd_resource_tile_mode(&rsc->b.b, psurf->u.tex.level);
enum a6xx_format format = fd6_color_format(pfmt, tile_mode);
uint32_t stride = fd_resource_pitch(rsc, psurf->u.tex.level);
uint32_t array_stride = fd_resource_layer_stride(rsc, psurf->u.tex.level);
enum a3xx_color_swap swap = fd6_color_swap(pfmt, rsc->layout.tile_mode);
enum a3xx_color_swap swap =
fd6_color_swap(pfmt, (enum a6xx_tile_mode)rsc->layout.tile_mode);
enum a3xx_msaa_samples samples = fd_msaa_samples(rsc->b.b.nr_samples);
OUT_REG(ring,

1
src/gallium/drivers/freedreno/a6xx/fd6_gmem.h
View file

@ -30,6 +30,7 @@
#include "pipe/p_context.h"
EXTERNC
void fd6_gmem_init(struct pipe_context *pctx);
#endif /* FD6_GMEM_H_ */

2
src/gallium/drivers/freedreno/a6xx/fd6_image.c
View file

@ -224,7 +224,7 @@ fd6_build_bindless_state(struct fd_context *ctx, enum pipe_shader_type shader,
"%s bindless", _mesa_shader_stage_to_abbrev(shader));
fd_bo_mark_for_dump(set->bo);
uint32_t *desc_buf = fd_bo_map(set->bo);
uint32_t *desc_buf = (uint32_t *)fd_bo_map(set->bo);
memcpy(desc_buf, set->descriptor, sizeof(set->descriptor));

4
src/gallium/drivers/freedreno/a6xx/fd6_image.h
View file

@ -30,10 +30,14 @@
#include "freedreno_context.h"
BEGINC;
struct fd_ringbuffer *
fd6_build_bindless_state(struct fd_context *ctx, enum pipe_shader_type shader,
bool append_fb_read) assert_dt;
void fd6_image_init(struct pipe_context *pctx);
ENDC;
#endif /* FD6_IMAGE_H_ */

8
src/gallium/drivers/freedreno/a6xx/fd6_program.c
View file

@ -791,7 +791,7 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_context *ctx,
}
OUT_PKT4(ring, REG_A6XX_PC_TESS_CNTL, 1);
uint32_t output;
enum a6xx_tess_output output;
if (ds->tess.point_mode)
output = TESS_POINTS;
else if (ds->tess.primitive_mode == TESS_PRIMITIVE_ISOLINES)
@ -1039,7 +1039,7 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_context *ctx,
COND(gs_reads_primid, A6XX_PC_GS_OUT_CNTL_PRIMITIVE_ID) |
A6XX_PC_GS_OUT_CNTL_CLIP_MASK(clip_cull_mask));
uint32_t output;
enum a6xx_tess_output output;
switch (gs->gs.output_primitive) {
case SHADER_PRIM_POINTS:
output = TESS_POINTS;
@ -1260,7 +1260,7 @@ emit_interp_state(struct fd_ringbuffer *ring, const struct fd6_program_state *st
/* If the last geometry shader doesn't statically write these, they're
* implicitly zero and the FS is supposed to read zero.
*/
if (ir3_find_output(last_shader, fs->inputs[j].slot) < 0 &&
if (ir3_find_output(last_shader, (gl_varying_slot)fs->inputs[j].slot) < 0 &&
(compmask & 0x1)) {
vinterp[loc / 16] |= INTERP_ZERO << ((loc % 16) * 2);
} else {
@ -1294,7 +1294,7 @@ fd6_program_create(void *data, struct ir3_shader_variant *bs,
struct ir3_shader_variant *fs,
const struct ir3_cache_key *key) in_dt
{
struct fd_context *ctx = fd_context(data);
struct fd_context *ctx = fd_context((struct pipe_context *)data);
struct fd_screen *screen = ctx->screen;
struct fd6_program_state *state = CALLOC_STRUCT(fd6_program_state);

4
src/gallium/drivers/freedreno/a6xx/fd6_program.h
View file

@ -99,6 +99,8 @@ fd6_last_shader(const struct fd6_program_state *state)
return state->vs;
}
BEGINC;
void fd6_emit_shader(struct fd_context *ctx, struct fd_ringbuffer *ring,
const struct ir3_shader_variant *so) assert_dt;
@ -106,4 +108,6 @@ struct fd_ringbuffer *fd6_program_interp_state(struct fd6_emit *emit) assert_dt;
void fd6_prog_init(struct pipe_context *pctx);
ENDC;
#endif /* FD6_PROGRAM_H_ */

17
src/gallium/drivers/freedreno/a6xx/fd6_query.c
View file

@ -355,12 +355,18 @@ struct PACKED fd6_primitives_sample {
};
DEFINE_CAST(fd_acc_query_sample, fd6_primitives_sample);
/* g++ is a picky about offsets that cannot be resolved at compile time, so
* roll our own __offsetof()
*/
#define __offsetof(type, field) \
({ type _x = {}; ((uint8_t *)&_x.field) - ((uint8_t *)&_x);})
#define primitives_relocw(ring, aq, field) \
OUT_RELOC(ring, fd_resource((aq)->prsc)->bo, \
offsetof(struct fd6_primitives_sample, field), 0, 0);
__offsetof(struct fd6_primitives_sample, field), 0, 0);
#define primitives_reloc(ring, aq, field) \
OUT_RELOC(ring, fd_resource((aq)->prsc)->bo, \
offsetof(struct fd6_primitives_sample, field), 0, 0);
__offsetof(struct fd6_primitives_sample, field), 0, 0);
#ifdef DEBUG_COUNTERS
static const unsigned counter_count = 10;
@ -586,7 +592,7 @@ struct fd_batch_query_data {
static void
perfcntr_resume(struct fd_acc_query *aq, struct fd_batch *batch) assert_dt
{
struct fd_batch_query_data *data = aq->query_data;
struct fd_batch_query_data *data = (struct fd_batch_query_data *)aq->query_data;
struct fd_screen *screen = data->screen;
struct fd_ringbuffer *ring = batch->draw;
@ -626,7 +632,7 @@ perfcntr_resume(struct fd_acc_query *aq, struct fd_batch *batch) assert_dt
static void
perfcntr_pause(struct fd_acc_query *aq, struct fd_batch *batch) assert_dt
{
struct fd_batch_query_data *data = aq->query_data;
struct fd_batch_query_data *data = (struct fd_batch_query_data *)aq->query_data;
struct fd_screen *screen = data->screen;
struct fd_ringbuffer *ring = batch->draw;
@ -667,7 +673,8 @@ perfcntr_accumulate_result(struct fd_acc_query *aq,
struct fd_acc_query_sample *s,
union pipe_query_result *result)
{
struct fd_batch_query_data *data = aq->query_data;
struct fd_batch_query_data *data =
(struct fd_batch_query_data *)aq->query_data;
struct fd6_query_sample *sp = fd6_query_sample(s);
for (unsigned i = 0; i < data->num_query_entries; i++) {

1
src/gallium/drivers/freedreno/a6xx/fd6_query.h
View file

@ -30,6 +30,7 @@
#include "pipe/p_context.h"
EXTERNC
void fd6_query_context_init(struct pipe_context *pctx);
#endif /* FD6_QUERY_H_ */

2
src/gallium/drivers/freedreno/a6xx/fd6_rasterizer.c
View file

@ -122,7 +122,7 @@ fd6_rasterizer_state_create(struct pipe_context *pctx,
void
fd6_rasterizer_state_delete(struct pipe_context *pctx, void *hwcso)
{
struct fd6_rasterizer_stateobj *so = hwcso;
struct fd6_rasterizer_stateobj *so = (struct fd6_rasterizer_stateobj *)hwcso;
for (unsigned i = 0; i < ARRAY_SIZE(so->stateobjs); i++)
if (so->stateobjs[i])

4
src/gallium/drivers/freedreno/a6xx/fd6_rasterizer.h
View file

@ -33,6 +33,8 @@
#include "freedreno_context.h"
BEGINC;
struct fd6_rasterizer_stateobj {
struct pipe_rasterizer_state base;
@ -69,4 +71,6 @@ fd6_rasterizer_state(struct fd_context *ctx, bool primitive_restart) assert_dt
return rasterizer->stateobjs[variant];
}
ENDC;
#endif /* FD6_RASTERIZER_H_ */

4
src/gallium/drivers/freedreno/a6xx/fd6_resource.c
View file

@ -265,7 +265,7 @@ static int
fill_ubwc_buffer_sizes(struct fd_resource *rsc)
{
struct pipe_resource *prsc = &rsc->b.b;
struct fdl_explicit_layout explicit = {
struct fdl_explicit_layout l = {
.offset = rsc->layout.slices[0].offset,
.pitch = rsc->layout.pitch0,
};
@ -278,7 +278,7 @@ fill_ubwc_buffer_sizes(struct fd_resource *rsc)
if (!fdl6_layout(&rsc->layout, prsc->format, fd_resource_nr_samples(prsc),
prsc->width0, prsc->height0, prsc->depth0,
prsc->last_level + 1, prsc->array_size, false, &explicit))
prsc->last_level + 1, prsc->array_size, false, &l))
return -1;
if (rsc->layout.size > fd_bo_size(rsc->bo))

5
src/gallium/drivers/freedreno/a6xx/fd6_resource.h
View file

@ -30,13 +30,14 @@
#include "freedreno_resource.h"
enum fd6_format_status {
FORMAT_OK,
DEMOTE_TO_LINEAR,
DEMOTE_TO_TILED,
};
BEGINC;
enum fd6_format_status fd6_check_valid_format(struct fd_resource *rsc,
enum pipe_format format);
void fd6_validate_format(struct fd_context *ctx, struct fd_resource *rsc,
@ -52,4 +53,6 @@ void fd6_emit_flag_reference(struct fd_ringbuffer *ring,
struct fd_resource *rsc, int level, int layer);
void fd6_resource_screen_init(struct pipe_screen *pscreen);
ENDC;
#endif /* FD6_RESOURCE_H_ */

7
src/gallium/drivers/freedreno/a6xx/fd6_screen.c
View file

@ -161,9 +161,10 @@ fd6_screen_init(struct pipe_screen *pscreen)
/* Currently only FB_READ forces GMEM path, mostly because we'd have to
* deal with cmdstream patching otherwise..
*/
screen->gmem_reason_mask = FD_GMEM_CLEARS_DEPTH_STENCIL |
FD_GMEM_DEPTH_ENABLED | FD_GMEM_STENCIL_ENABLED |
FD_GMEM_BLEND_ENABLED | FD_GMEM_LOGICOP_ENABLED;
screen->gmem_reason_mask = (enum fd_gmem_reason)(
FD_GMEM_CLEARS_DEPTH_STENCIL |
FD_GMEM_DEPTH_ENABLED | FD_GMEM_STENCIL_ENABLED |
FD_GMEM_BLEND_ENABLED | FD_GMEM_LOGICOP_ENABLED);
pscreen->context_create = fd6_context_create;
pscreen->is_format_supported = fd6_screen_is_format_supported;

2
src/gallium/drivers/freedreno/a6xx/fd6_screen.h
View file

@ -30,6 +30,6 @@
#include "pipe/p_screen.h"
void fd6_screen_init(struct pipe_screen *pscreen);
EXTERNC void fd6_screen_init(struct pipe_screen *pscreen);
#endif /* FD6_SCREEN_H_ */

42
src/gallium/drivers/freedreno/a6xx/fd6_texture.c
View file

@ -45,7 +45,7 @@ static void fd6_texture_state_destroy(struct fd6_texture_state *state);
static void
remove_tex_entry(struct fd6_context *fd6_ctx, struct hash_entry *entry)
{
struct fd6_texture_state *tex = entry->data;
struct fd6_texture_state *tex = (struct fd6_texture_state *)entry->data;
_mesa_hash_table_remove(fd6_ctx->tex_cache, entry);
fd6_texture_state_destroy(tex);
}
@ -73,7 +73,7 @@ tex_clamp(unsigned wrap, bool *needs_border)
*/
default:
DBG("invalid wrap: %u", wrap);
return 0;
return (enum a6xx_tex_clamp)0;
}
}
@ -87,7 +87,7 @@ tex_filter(unsigned filter, bool aniso)
return aniso ? A6XX_TEX_ANISO : A6XX_TEX_LINEAR;
default:
DBG("invalid filter: %u", filter);
return 0;
return (enum a6xx_tex_filter)0;
}
}
@ -206,15 +206,15 @@ setup_border_color(struct fd_screen *screen,
static uint32_t
bcolor_key_hash(const void *_key)
{
const struct fd6_bcolor_entry *key = _key;
const struct fd6_bcolor_entry *key = (const struct fd6_bcolor_entry *)_key;
return XXH32(key, sizeof(*key), 0);
}
static bool
bcolor_key_equals(const void *_a, const void *_b)
{
const struct fd6_bcolor_entry *a = _a;
const struct fd6_bcolor_entry *b = _b;
const struct fd6_bcolor_entry *a = (const struct fd6_bcolor_entry *)_a;
const struct fd6_bcolor_entry *b = (const struct fd6_bcolor_entry *)_b;
return memcmp(a, b, sizeof(struct fd6_bcolor_entry)) == 0;
}
@ -222,7 +222,8 @@ static unsigned
get_bcolor_offset(struct fd_context *ctx, const struct pipe_sampler_state *sampler)
{
struct fd6_context *fd6_ctx = fd6_context(ctx);
struct fd6_bcolor_entry *entries = fd_bo_map(fd6_ctx->bcolor_mem);
struct fd6_bcolor_entry *entries =
(struct fd6_bcolor_entry *)fd_bo_map(fd6_ctx->bcolor_mem);
struct fd6_bcolor_entry key = {};
setup_border_color(ctx->screen, sampler, &key);
@ -273,7 +274,7 @@ fd6_sampler_state_create(struct pipe_context *pctx,
COND(miplinear, A6XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR) |
A6XX_TEX_SAMP_0_XY_MAG(tex_filter(cso->mag_img_filter, aniso)) |
A6XX_TEX_SAMP_0_XY_MIN(tex_filter(cso->min_img_filter, aniso)) |
A6XX_TEX_SAMP_0_ANISO(aniso) |
A6XX_TEX_SAMP_0_ANISO((enum a6xx_tex_aniso)aniso) |
A6XX_TEX_SAMP_0_WRAP_S(tex_clamp(cso->wrap_s, &needs_border)) |
A6XX_TEX_SAMP_0_WRAP_T(tex_clamp(cso->wrap_t, &needs_border)) |
A6XX_TEX_SAMP_0_WRAP_R(tex_clamp(cso->wrap_r, &needs_border));
@ -290,7 +291,7 @@ fd6_sampler_state_create(struct pipe_context *pctx,
if (cso->compare_mode)
so->texsamp1 |=
A6XX_TEX_SAMP_1_COMPARE_FUNC(cso->compare_func); /* maps 1:1 */
A6XX_TEX_SAMP_1_COMPARE_FUNC((enum adreno_compare_func)cso->compare_func); /* maps 1:1 */
if (needs_border)
so->texsamp2 = A6XX_TEX_SAMP_2_BCOLOR(get_bcolor_offset(ctx, cso));
@ -310,12 +311,12 @@ fd6_sampler_state_delete(struct pipe_context *pctx, void *hwcso)
{
struct fd_context *ctx = fd_context(pctx);
struct fd6_context *fd6_ctx = fd6_context(ctx);
struct fd6_sampler_stateobj *samp = hwcso;
struct fd6_sampler_stateobj *samp = (struct fd6_sampler_stateobj *)hwcso;
fd_screen_lock(ctx->screen);
hash_table_foreach (fd6_ctx->tex_cache, entry) {
struct fd6_texture_state *state = entry->data;
struct fd6_texture_state *state = (struct fd6_texture_state *)entry->data;
for (unsigned i = 0; i < ARRAY_SIZE(state->key.samp_seqno); i++) {
if (samp->seqno == state->key.samp_seqno[i]) {
@ -414,7 +415,7 @@ fd6_sampler_view_update(struct fd_context *ctx,
struct fd_resource *plane1 = fd_resource(rsc->b.b.next);
struct fd_resource *plane2 =
plane1 ? fd_resource(plane1->b.b.next) : NULL;
static const struct fdl_layout dummy_layout = {0};
static const struct fdl_layout dummy_layout = {};
const struct fdl_layout *layouts[3] = {
&rsc->layout,
plane1 ? &plane1->layout : &dummy_layout,
@ -481,7 +482,7 @@ fd6_sampler_view_destroy(struct pipe_context *pctx,
fd_screen_lock(ctx->screen);
hash_table_foreach (fd6_ctx->tex_cache, entry) {
struct fd6_texture_state *state = entry->data;
struct fd6_texture_state *state = (struct fd6_texture_state *)entry->data;
for (unsigned i = 0; i < ARRAY_SIZE(state->key.view_seqno); i++) {
if (view->seqno == state->key.view_seqno[i]) {
@ -501,15 +502,15 @@ fd6_sampler_view_destroy(struct pipe_context *pctx,
static uint32_t
tex_key_hash(const void *_key)
{
const struct fd6_texture_key *key = _key;
const struct fd6_texture_key *key = (const struct fd6_texture_key *)_key;
return XXH32(key, sizeof(*key), 0);
}
static bool
tex_key_equals(const void *_a, const void *_b)
{
const struct fd6_texture_key *a = _a;
const struct fd6_texture_key *b = _b;
const struct fd6_texture_key *a = (const struct fd6_texture_key *)_a;
const struct fd6_texture_key *b = (const struct fd6_texture_key *)_b;
return memcmp(a, b, sizeof(struct fd6_texture_key)) == 0;
}
@ -684,7 +685,7 @@ handle_invalidates(struct fd_context *ctx)
fd_screen_lock(ctx->screen);
hash_table_foreach (fd6_ctx->tex_cache, entry) {
struct fd6_texture_state *state = entry->data;
struct fd6_texture_state *state = (struct fd6_texture_state *)entry->data;
if (state->invalidate)
remove_tex_entry(fd6_ctx, entry);
@ -751,7 +752,7 @@ fd6_texture_state(struct fd_context *ctx, enum pipe_shader_type type)
_mesa_hash_table_search_pre_hashed(fd6_ctx->tex_cache, hash, &key);
if (entry) {
state = entry->data;
state = (struct fd6_texture_state *)entry->data;
for (unsigned i = 0; i < tex->num_textures; i++) {
uint16_t seqno = tex->textures[i] ?
fd_resource(tex->textures[i]->texture)->seqno : 0;
@ -802,13 +803,14 @@ fd6_rebind_resource(struct fd_context *ctx, struct fd_resource *rsc) assert_dt
struct fd6_context *fd6_ctx = fd6_context(ctx);
hash_table_foreach (fd6_ctx->tex_cache, entry) {
struct fd6_texture_state *state = entry->data;
struct fd6_texture_state *state = (struct fd6_texture_state *)entry->data;
STATIC_ASSERT(ARRAY_SIZE(state->view_rsc_seqno) == ARRAY_SIZE(state->key.view_seqno));
for (unsigned i = 0; i < ARRAY_SIZE(state->view_rsc_seqno); i++) {
if (rsc->seqno == state->view_rsc_seqno[i]) {
struct fd6_texture_state *tex = entry->data;
struct fd6_texture_state *tex =
(struct fd6_texture_state *)entry->data;
tex->invalidate = true;
fd6_ctx->tex_cache_needs_invalidate = true;
}

5
src/gallium/drivers/freedreno/a6xx/fd6_texture.h
View file

@ -36,6 +36,9 @@
#include "fd6_context.h"
#include "fdl/fd6_format_table.h"
BEGINC;
/* Border color layout is diff from a4xx/a5xx.. if it turns out to be
* the same as a6xx then move this somewhere common ;-)
*
@ -127,4 +130,6 @@ struct fd6_texture_state {
struct fd6_texture_state *
fd6_texture_state(struct fd_context *ctx, enum pipe_shader_type type) assert_dt;
ENDC;
#endif /* FD6_TEXTURE_H_ */

1
src/gallium/drivers/freedreno/a6xx/fd6_vsc.h
View file

@ -24,6 +24,7 @@
#ifndef FD6_VSC_H_
#define FD6_VSC_H_
EXTERNC
void fd6_vsc_update_sizes(struct fd_batch *batch,
const struct pipe_draw_info *info,
const struct pipe_draw_start_count_bias *draw);

15
src/gallium/drivers/freedreno/a6xx/fd6_zsa.c
View file

@ -106,7 +106,7 @@ fd6_zsa_state_create(struct pipe_context *pctx,
so->writes_z = util_writes_depth(cso);
so->rb_depth_cntl |=
A6XX_RB_DEPTH_CNTL_ZFUNC(cso->depth_func); /* maps 1:1 */
A6XX_RB_DEPTH_CNTL_ZFUNC((enum adreno_compare_func)cso->depth_func); /* maps 1:1 */
if (cso->depth_enabled) {
so->rb_depth_cntl |=
@ -167,12 +167,12 @@ fd6_zsa_state_create(struct pipe_context *pctx,
* stencil test we don't really know what the updates to the
* depth buffer will be.
*/
update_lrz_stencil(so, s->func, util_writes_stencil(s));
update_lrz_stencil(so, (enum pipe_compare_func)s->func, util_writes_stencil(s));
so->rb_stencil_control |=
A6XX_RB_STENCIL_CONTROL_STENCIL_READ |
A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
A6XX_RB_STENCIL_CONTROL_FUNC(s->func) | /* maps 1:1 */
A6XX_RB_STENCIL_CONTROL_FUNC((enum adreno_compare_func)s->func) | /* maps 1:1 */
A6XX_RB_STENCIL_CONTROL_FAIL(fd_stencil_op(s->fail_op)) |
A6XX_RB_STENCIL_CONTROL_ZPASS(fd_stencil_op(s->zpass_op)) |
A6XX_RB_STENCIL_CONTROL_ZFAIL(fd_stencil_op(s->zfail_op));
@ -183,11 +183,11 @@ fd6_zsa_state_create(struct pipe_context *pctx,
if (cso->stencil[1].enabled) {
const struct pipe_stencil_state *bs = &cso->stencil[1];
update_lrz_stencil(so, bs->func, util_writes_stencil(bs));
update_lrz_stencil(so, (enum pipe_compare_func)bs->func, util_writes_stencil(bs));
so->rb_stencil_control |=
A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF |
A6XX_RB_STENCIL_CONTROL_FUNC_BF(bs->func) | /* maps 1:1 */
A6XX_RB_STENCIL_CONTROL_FUNC_BF((enum adreno_compare_func)bs->func) | /* maps 1:1 */
A6XX_RB_STENCIL_CONTROL_FAIL_BF(fd_stencil_op(bs->fail_op)) |
A6XX_RB_STENCIL_CONTROL_ZPASS_BF(fd_stencil_op(bs->zpass_op)) |
A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(fd_stencil_op(bs->zfail_op));
@ -210,7 +210,8 @@ fd6_zsa_state_create(struct pipe_context *pctx,
so->rb_alpha_control =
A6XX_RB_ALPHA_CONTROL_ALPHA_TEST |
A6XX_RB_ALPHA_CONTROL_ALPHA_REF(ref) |
A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(cso->alpha_func);
A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(
(enum adreno_compare_func)cso->alpha_func);
}
for (int i = 0; i < 4; i++) {
@ -243,7 +244,7 @@ fd6_zsa_state_create(struct pipe_context *pctx,
void
fd6_zsa_state_delete(struct pipe_context *pctx, void *hwcso)
{
struct fd6_zsa_stateobj *so = hwcso;
struct fd6_zsa_stateobj *so = (struct fd6_zsa_stateobj *)hwcso;
for (int i = 0; i < ARRAY_SIZE(so->stateobj); i++)
fd_ringbuffer_del(so->stateobj[i]);

4
src/gallium/drivers/freedreno/a6xx/fd6_zsa.h
View file

@ -35,6 +35,8 @@
#include "fd6_context.h"
BEGINC;
#define FD6_ZSA_NO_ALPHA (1 << 0)
#define FD6_ZSA_DEPTH_CLAMP (1 << 1)
@ -85,4 +87,6 @@ void *fd6_zsa_state_create(struct pipe_context *pctx,
void fd6_zsa_state_delete(struct pipe_context *pctx, void *hwcso);
ENDC;
#endif /* FD6_ZSA_H_ */

4
src/gallium/drivers/freedreno/freedreno_batch_cache.h
View file

@ -31,6 +31,8 @@
#include "freedreno_util.h"
BEGINC;
struct fd_resource;
struct fd_batch;
struct fd_context;
@ -81,4 +83,6 @@ struct fd_batch *
fd_batch_from_fb(struct fd_context *ctx,
const struct pipe_framebuffer_state *pfb) assert_dt;
ENDC;
#endif /* FREEDRENO_BATCH_CACHE_H_ */

4
src/gallium/drivers/freedreno/freedreno_blitter.h
View file

@ -32,6 +32,8 @@
#include "freedreno_context.h"
BEGINC;
bool fd_blitter_blit(struct fd_context *ctx,
const struct pipe_blit_info *info) assert_dt;
@ -70,4 +72,6 @@ bool fd_blit(struct pipe_context *pctx,
} \
} while (0)
ENDC;
#endif /* FREEDRENO_BLIT_H_ */

3
src/gallium/drivers/freedreno/freedreno_context.h
View file

@ -688,8 +688,7 @@ fd_context_all_clean(struct fd_context *ctx) assert_dt
* bit.
*/
static inline void
fd_context_add_map(struct fd_context *ctx, enum fd_dirty_3d_state dirty,
uint32_t gen_dirty)
fd_context_add_map(struct fd_context *ctx, uint32_t dirty, uint32_t gen_dirty)
{
u_foreach_bit (b, dirty) {
ctx->gen_dirty_map[b] |= gen_dirty;

2
src/gallium/drivers/freedreno/freedreno_draw.h
View file

@ -39,6 +39,7 @@ struct fd_ringbuffer;
void fd_draw_init(struct pipe_context *pctx);
#ifndef __cplusplus
static inline void
fd_draw(struct fd_batch *batch, struct fd_ringbuffer *ring,
enum pc_di_primtype primtype, enum pc_di_vis_cull_mode vismode,
@ -170,6 +171,7 @@ fd_draw_emit(struct fd_batch *batch, struct fd_ringbuffer *ring,
info->instance_count - 1, idx_type, idx_size, idx_offset,
idx_buffer);
}
#endif
static inline void
fd_blend_tracking(struct fd_context *ctx)

5
src/gallium/drivers/freedreno/freedreno_fence.h
View file

@ -30,8 +30,11 @@
#include "pipe/p_context.h"
#include "util/u_queue.h"
#include "common/freedreno_common.h"
#include "drm/freedreno_drmif.h"
BEGINC;
struct pipe_fence_handle {
struct pipe_reference reference;
@ -109,4 +112,6 @@ struct pipe_fence_handle *
fd_pipe_fence_create_unflushed(struct pipe_context *pctx,
struct tc_unflushed_batch_token *tc_token);
ENDC;
#endif /* FREEDRENO_FENCE_H_ */

4
src/gallium/drivers/freedreno/freedreno_gmem.h
View file

@ -32,6 +32,8 @@
#include "freedreno_util.h"
BEGINC;
/* per-pipe configuration for hw binning: */
struct fd_vsc_pipe {
uint8_t x, y, w, h; /* VSC_PIPE[p].CONFIG */
@ -96,4 +98,6 @@ struct pipe_screen;
void fd_gmem_screen_init(struct pipe_screen *pscreen);
void fd_gmem_screen_fini(struct pipe_screen *pscreen);
ENDC;
#endif /* FREEDRENO_GMEM_H_ */

6
src/gallium/drivers/freedreno/freedreno_program.h
View file

@ -29,7 +29,13 @@
#include "pipe/p_context.h"
#include "common/freedreno_common.h"
BEGINC;
void fd_prog_init(struct pipe_context *pctx);
void fd_prog_fini(struct pipe_context *pctx);
ENDC;
#endif /* FREEDRENO_PROGRAM_H_ */

4
src/gallium/drivers/freedreno/freedreno_query_acc.h
View file

@ -33,6 +33,8 @@
#include "freedreno_query.h"
#include "freedreno_resource.h"
BEGINC;
/*
* Accumulated HW Queries:
*
@ -142,4 +144,6 @@ copy_result(struct fd_ringbuffer *ring, enum pipe_query_value_type result_type,
OUT_RELOC(ring, src->bo, src_offset, 0, 0);
}
ENDC;
#endif /* FREEDRENO_QUERY_ACC_H_ */

4
src/gallium/drivers/freedreno/freedreno_resource.h
View file

@ -37,6 +37,8 @@
#include "freedreno_batch.h"
#include "freedreno_util.h"
BEGINC;
#define PRSC_FMT \
"p: target=%s, format=%s, %ux%ux%u, " \
"array_size=%u, last_level=%u, " \
@ -400,4 +402,6 @@ fdl_type_from_pipe_target(enum pipe_texture_target target) {
}
}
ENDC;
#endif /* FREEDRENO_RESOURCE_H_ */

4
src/gallium/drivers/freedreno/freedreno_state.h
View file

@ -30,6 +30,8 @@
#include "pipe/p_context.h"
#include "freedreno_context.h"
BEGINC;
static inline bool
fd_depth_enabled(struct fd_context *ctx) assert_dt
{
@ -77,4 +79,6 @@ void fd_set_framebuffer_state(struct pipe_context *pctx,
void fd_state_init(struct pipe_context *pctx);
ENDC;
#endif /* FREEDRENO_STATE_H_ */

4
src/gallium/drivers/freedreno/freedreno_texture.h
View file

@ -29,6 +29,8 @@
#include "pipe/p_context.h"
BEGINC;
void fd_sampler_states_bind(struct pipe_context *pctx,
enum pipe_shader_type shader, unsigned start,
unsigned nr, void **hwcso);
@ -72,4 +74,6 @@ struct fd_texture_stateobj;
void fd_setup_border_colors(struct fd_texture_stateobj *tex, void *ptr,
unsigned offset);
ENDC;
#endif /* FREEDRENO_TEXTURE_H_ */

4
src/gallium/drivers/freedreno/ir3/ir3_cache.h
View file

@ -31,6 +31,8 @@
#include "ir3/ir3_shader.h"
BEGINC;
/*
* An in-memory cache for mapping shader state objects plus shader key to
* hw specific state object for the specified shader variant. This is to
@ -85,4 +87,6 @@ struct ir3_program_state *ir3_cache_lookup(struct ir3_cache *cache,
*/
void ir3_cache_invalidate(struct ir3_cache *cache, void *stobj);
ENDC;
#endif /* IR3_CACHE_H_ */

9
src/gallium/drivers/freedreno/ir3/ir3_const.h
View file

@ -190,8 +190,9 @@ ir3_emit_user_consts(const struct ir3_shader_variant *v,
assert((offset % 16) == 0);
if (cb->user_buffer) {
emit_const_user(ring, v, state->range[i].offset / 4, size / 4,
cb->user_buffer + state->range[i].start);
uint8_t *p = (uint8_t *)cb->user_buffer;
p += state->range[i].start;
emit_const_user(ring, v, state->range[i].offset / 4, size / 4, (uint32_t *)p);
} else {
emit_const_prsc(ring, v, state->range[i].offset / 4, offset, size / 4,
cb->buffer);
@ -408,7 +409,7 @@ emit_common_consts(const struct ir3_shader_variant *v,
* different state-objects we could avoid this.
*/
if (dirty && is_stateobj(ring))
dirty = ~0;
dirty = (enum fd_dirty_shader_state)~0;
if (dirty & (FD_DIRTY_SHADER_PROG | FD_DIRTY_SHADER_CONST)) {
struct fd_constbuf_stateobj *constbuf;
@ -444,7 +445,7 @@ emit_kernel_params(struct fd_context *ctx, const struct ir3_shader_variant *v,
ring_wfi(ctx->batch, ring);
emit_const_user(ring, v, offset * 4,
align(v->cs.req_input_mem, 4),
info->input);
(uint32_t *)info->input);
}
}

6
src/gallium/drivers/freedreno/ir3/ir3_gallium.h
View file

@ -33,6 +33,8 @@
#include "freedreno_util.h"
BEGINC;
/**
* The ir3 hwcso type, use ir3_get_shader() to dereference the
* underlying ir3_shader
@ -67,7 +69,7 @@ static inline bool
ir3_point_sprite(const struct ir3_shader_variant *fs, int i,
uint32_t sprite_coord_enable, bool *coord_mode)
{
gl_varying_slot slot = fs->inputs[i].slot;
gl_varying_slot slot = (gl_varying_slot)fs->inputs[i].slot;
switch (slot) {
case VARYING_SLOT_PNTC:
*coord_mode = true;
@ -82,4 +84,6 @@ ir3_point_sprite(const struct ir3_shader_variant *fs, int i,
void ir3_update_max_tf_vtx(struct fd_context *ctx,
const struct ir3_shader_variant *v) assert_dt;
ENDC;
#endif /* IR3_GALLIUM_H_ */