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i965: Add a new infrastructure for generating Broadwell shader assembly.
This replaces the brw_eu_emit.c layer for Broadwell. It will be
used by both the vector and scalar shader backends.
v2: Port to use the C-based instruction representation.
v3: Fix destination register type for CMP.
v4: Pass brw to gen8_instruction functions (required by rebase).
v5: Remove bogus assertion on math instructions (caught by Piglit).
v6: Remove more restrictions on math instructions (caught by Eric).
Make ADDC and SUBB helpers set accumulator writes, like MAC and
MACH (caught by Matt).
v7: Don't implicitly force ALU3 operations to SIMD8 (we've been able
to do SIMD16 versions since Haswell, but didn't when I originally
wrote this code).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
This commit is contained in:
Kenneth Graunke
parent
8ea4b16eea
commit
f8035ba036
3 changed files with 842 additions and 0 deletions
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@ -140,5 +140,6 @@ i965_FILES = \
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gen7_wm_state.c \
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gen7_wm_surface_state.c \
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gen8_disasm.c \
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gen8_generator.cpp \
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gen8_instruction.c \
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$()
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643
src/mesa/drivers/dri/i965/gen8_generator.cpp
Normal file
643
src/mesa/drivers/dri/i965/gen8_generator.cpp
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@ -0,0 +1,643 @@
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/*
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* Copyright © 2012 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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/** @file gen8_generator.cpp
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*
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* Code generation for Gen8+ hardware, replacing the brw_eu_emit.c layer.
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*/
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extern "C" {
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#include "main/compiler.h"
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#include "main/macros.h"
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#include "brw_context.h"
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} /* extern "C" */
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#include "glsl/ralloc.h"
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#include "brw_eu.h"
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#include "brw_reg.h"
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#include "gen8_generator.h"
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gen8_generator::gen8_generator(struct brw_context *brw,
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struct gl_shader_program *shader_prog,
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struct gl_program *prog,
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void *mem_ctx)
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: shader_prog(shader_prog), prog(prog), brw(brw), mem_ctx(mem_ctx)
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{
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ctx = &brw->ctx;
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memset(&default_state, 0, sizeof(default_state));
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default_state.mask_control = BRW_MASK_ENABLE;
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store_size = 1024;
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store = rzalloc_array(mem_ctx, gen8_instruction, store_size);
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nr_inst = 0;
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next_inst_offset = 0;
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/* Set up the control flow stacks. */
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if_stack_depth = 0;
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if_stack_array_size = 16;
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if_stack = rzalloc_array(mem_ctx, int, if_stack_array_size);
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loop_stack_depth = 0;
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loop_stack_array_size = 16;
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loop_stack = rzalloc_array(mem_ctx, int, loop_stack_array_size);
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}
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gen8_generator::~gen8_generator()
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{
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}
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gen8_instruction *
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gen8_generator::next_inst(unsigned opcode)
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{
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gen8_instruction *inst;
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if (nr_inst + 1 > unsigned(store_size)) {
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store_size <<= 1;
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store = reralloc(mem_ctx, store, gen8_instruction, store_size);
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assert(store);
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}
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next_inst_offset += 16;
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inst = &store[nr_inst++];
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memset(inst, 0, sizeof(gen8_instruction));
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gen8_set_opcode(inst, opcode);
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gen8_set_exec_size(inst, default_state.exec_size);
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gen8_set_access_mode(inst, default_state.access_mode);
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gen8_set_mask_control(inst, default_state.mask_control);
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gen8_set_cond_modifier(inst, default_state.conditional_mod);
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gen8_set_pred_control(inst, default_state.predicate);
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gen8_set_pred_inv(inst, default_state.predicate_inverse);
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gen8_set_saturate(inst, default_state.saturate);
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gen8_set_flag_subreg_nr(inst, default_state.flag_subreg_nr);
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return inst;
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}
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#define ALU1(OP) \
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gen8_instruction * \
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gen8_generator::OP(struct brw_reg dst, struct brw_reg src) \
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{ \
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gen8_instruction *inst = next_inst(BRW_OPCODE_##OP); \
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gen8_set_dst(brw, inst, dst); \
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gen8_set_src0(brw, inst, src); \
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return inst; \
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}
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#define ALU2(OP) \
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gen8_instruction * \
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gen8_generator::OP(struct brw_reg dst, struct brw_reg s0, struct brw_reg s1) \
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{ \
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gen8_instruction *inst = next_inst(BRW_OPCODE_##OP); \
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gen8_set_dst(brw, inst, dst); \
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gen8_set_src0(brw, inst, s0); \
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gen8_set_src1(brw, inst, s1); \
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return inst; \
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}
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#define ALU2_ACCUMULATE(OP) \
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gen8_instruction * \
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gen8_generator::OP(struct brw_reg dst, struct brw_reg s0, struct brw_reg s1) \
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{ \
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gen8_instruction *inst = next_inst(BRW_OPCODE_##OP); \
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gen8_set_dst(brw, inst, dst); \
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gen8_set_src0(brw, inst, s0); \
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gen8_set_src1(brw, inst, s1); \
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gen8_set_acc_wr_control(inst, true); \
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return inst; \
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}
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#define ALU3(OP) \
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gen8_instruction * \
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gen8_generator::OP(struct brw_reg dst, struct brw_reg s0, \
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struct brw_reg s1, struct brw_reg s2) \
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{ \
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return alu3(BRW_OPCODE_##OP, dst, s0, s1, s2); \
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}
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#define ALU3F(OP) \
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gen8_instruction * \
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gen8_generator::OP(struct brw_reg dst, struct brw_reg s0, \
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struct brw_reg s1, struct brw_reg s2) \
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{ \
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assert(dst.type == BRW_REGISTER_TYPE_F); \
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assert(s0.type == BRW_REGISTER_TYPE_F); \
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assert(s1.type == BRW_REGISTER_TYPE_F); \
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assert(s2.type == BRW_REGISTER_TYPE_F); \
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return alu3(BRW_OPCODE_##OP, dst, s0, s1, s2); \
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}
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ALU2(ADD)
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ALU2(AND)
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ALU2(ASR)
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ALU3(BFE)
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ALU2(BFI1)
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ALU3(BFI2)
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ALU1(F32TO16)
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ALU1(F16TO32)
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ALU1(BFREV)
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ALU1(CBIT)
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ALU2_ACCUMULATE(ADDC)
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ALU2_ACCUMULATE(SUBB)
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ALU2(DP2)
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ALU2(DP3)
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ALU2(DP4)
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ALU2(DPH)
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ALU1(FBH)
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ALU1(FBL)
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ALU1(FRC)
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ALU2(LINE)
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ALU3F(LRP)
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ALU3F(MAD)
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ALU2(MUL)
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ALU1(MOV)
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ALU1(NOT)
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ALU2(OR)
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ALU2(PLN)
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ALU1(RNDD)
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ALU1(RNDE)
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ALU1(RNDZ)
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ALU2_ACCUMULATE(MAC)
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ALU2_ACCUMULATE(MACH)
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ALU2(SEL)
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ALU2(SHL)
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ALU2(SHR)
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ALU2(XOR)
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gen8_instruction *
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gen8_generator::CMP(struct brw_reg dst, unsigned conditional,
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struct brw_reg src0, struct brw_reg src1)
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{
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gen8_instruction *inst = next_inst(BRW_OPCODE_CMP);
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gen8_set_cond_modifier(inst, conditional);
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/* The CMP instruction appears to behave erratically for floating point
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* sources unless the destination type is also float. Overriding it to
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* match src0 makes it work in all cases.
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*/
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dst.type = src0.type;
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gen8_set_dst(brw, inst, dst);
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gen8_set_src0(brw, inst, src0);
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gen8_set_src1(brw, inst, src1);
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return inst;
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}
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static int
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get_3src_subreg_nr(struct brw_reg reg)
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{
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if (reg.vstride == BRW_VERTICAL_STRIDE_0) {
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assert(brw_is_single_value_swizzle(reg.dw1.bits.swizzle));
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return reg.subnr / 4 + BRW_GET_SWZ(reg.dw1.bits.swizzle, 0);
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} else {
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return reg.subnr / 4;
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}
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}
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gen8_instruction *
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gen8_generator::alu3(unsigned opcode,
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struct brw_reg dst,
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struct brw_reg src0,
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struct brw_reg src1,
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struct brw_reg src2)
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{
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/* MRFs haven't existed since Gen7, so we better not be using them. */
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if (dst.file == BRW_MESSAGE_REGISTER_FILE) {
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dst.file = BRW_GENERAL_REGISTER_FILE;
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dst.nr += GEN7_MRF_HACK_START;
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}
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gen8_instruction *inst = next_inst(opcode);
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assert(gen8_access_mode(inst) == BRW_ALIGN_16);
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assert(dst.file == BRW_GENERAL_REGISTER_FILE);
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assert(dst.nr < 128);
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assert(dst.address_mode == BRW_ADDRESS_DIRECT);
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assert(dst.type == BRW_REGISTER_TYPE_F ||
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dst.type == BRW_REGISTER_TYPE_D ||
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dst.type == BRW_REGISTER_TYPE_UD);
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gen8_set_dst_3src_reg_nr(inst, dst.nr);
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gen8_set_dst_3src_subreg_nr(inst, dst.subnr / 16);
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gen8_set_dst_3src_writemask(inst, dst.dw1.bits.writemask);
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assert(src0.file == BRW_GENERAL_REGISTER_FILE);
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assert(src0.address_mode == BRW_ADDRESS_DIRECT);
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assert(src0.nr < 128);
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gen8_set_src0_3src_swizzle(inst, src0.dw1.bits.swizzle);
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gen8_set_src0_3src_subreg_nr(inst, get_3src_subreg_nr(src0));
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gen8_set_src0_3src_rep_ctrl(inst, src0.vstride == BRW_VERTICAL_STRIDE_0);
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gen8_set_src0_3src_reg_nr(inst, src0.nr);
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gen8_set_src0_3src_abs(inst, src0.abs);
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gen8_set_src0_3src_negate(inst, src0.negate);
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assert(src1.file == BRW_GENERAL_REGISTER_FILE);
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assert(src1.address_mode == BRW_ADDRESS_DIRECT);
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assert(src1.nr < 128);
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gen8_set_src1_3src_swizzle(inst, src1.dw1.bits.swizzle);
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gen8_set_src1_3src_subreg_nr(inst, get_3src_subreg_nr(src1));
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gen8_set_src1_3src_rep_ctrl(inst, src1.vstride == BRW_VERTICAL_STRIDE_0);
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gen8_set_src1_3src_reg_nr(inst, src1.nr);
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gen8_set_src1_3src_abs(inst, src1.abs);
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gen8_set_src1_3src_negate(inst, src1.negate);
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assert(src2.file == BRW_GENERAL_REGISTER_FILE);
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assert(src2.address_mode == BRW_ADDRESS_DIRECT);
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assert(src2.nr < 128);
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gen8_set_src2_3src_swizzle(inst, src2.dw1.bits.swizzle);
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gen8_set_src2_3src_subreg_nr(inst, get_3src_subreg_nr(src2));
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gen8_set_src2_3src_rep_ctrl(inst, src2.vstride == BRW_VERTICAL_STRIDE_0);
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gen8_set_src2_3src_reg_nr(inst, src2.nr);
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gen8_set_src2_3src_abs(inst, src2.abs);
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gen8_set_src2_3src_negate(inst, src2.negate);
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/* Set both the source and destination types based on dst.type, ignoring
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* the source register types. The MAD and LRP emitters both ensure that
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* all register types are float. The BFE and BFI2 emitters, however, may
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* send us mixed D and UD source types and want us to ignore that.
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*/
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switch (dst.type) {
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case BRW_REGISTER_TYPE_F:
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gen8_set_src_3src_type(inst, BRW_3SRC_TYPE_F);
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gen8_set_dst_3src_type(inst, BRW_3SRC_TYPE_F);
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break;
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case BRW_REGISTER_TYPE_D:
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gen8_set_src_3src_type(inst, BRW_3SRC_TYPE_D);
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gen8_set_dst_3src_type(inst, BRW_3SRC_TYPE_D);
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break;
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case BRW_REGISTER_TYPE_UD:
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gen8_set_src_3src_type(inst, BRW_3SRC_TYPE_UD);
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gen8_set_dst_3src_type(inst, BRW_3SRC_TYPE_UD);
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break;
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}
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return inst;
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}
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gen8_instruction *
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gen8_generator::math(unsigned math_function,
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struct brw_reg dst,
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struct brw_reg src0)
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{
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gen8_instruction *inst = next_inst(BRW_OPCODE_MATH);
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assert(dst.hstride == src0.hstride);
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gen8_set_math_function(inst, math_function);
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gen8_set_dst(brw, inst, dst);
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gen8_set_src0(brw, inst, src0);
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return inst;
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}
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gen8_instruction *
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gen8_generator::MATH(unsigned math_function,
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struct brw_reg dst,
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struct brw_reg src0)
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{
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assert(src0.type == BRW_REGISTER_TYPE_F);
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gen8_instruction *inst = math(math_function, dst, src0);
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return inst;
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}
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gen8_instruction *
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gen8_generator::MATH(unsigned math_function,
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struct brw_reg dst,
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struct brw_reg src0,
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struct brw_reg src1)
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{
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bool int_math =
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math_function == BRW_MATH_FUNCTION_INT_DIV_QUOTIENT ||
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math_function == BRW_MATH_FUNCTION_INT_DIV_REMAINDER ||
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math_function == BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER;
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if (int_math) {
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assert(src0.type != BRW_REGISTER_TYPE_F);
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assert(src1.type != BRW_REGISTER_TYPE_F);
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} else {
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assert(src0.type == BRW_REGISTER_TYPE_F);
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}
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gen8_instruction *inst = math(math_function, dst, src0);
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gen8_set_src1(brw, inst, src1);
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return inst;
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}
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gen8_instruction *
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gen8_generator::MOV_RAW(struct brw_reg dst, struct brw_reg src0)
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{
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gen8_instruction *inst = next_inst(BRW_OPCODE_MOV);
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gen8_set_dst(brw, inst, retype(dst, BRW_REGISTER_TYPE_UD));
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gen8_set_src0(brw, inst, retype(src0, BRW_REGISTER_TYPE_UD));
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gen8_set_mask_control(inst, BRW_MASK_DISABLE);
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return inst;
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}
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gen8_instruction *
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gen8_generator::NOP()
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{
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return next_inst(BRW_OPCODE_NOP);
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}
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void
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gen8_generator::push_if_stack(gen8_instruction *inst)
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{
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if_stack[if_stack_depth] = inst - store;
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++if_stack_depth;
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if (if_stack_array_size <= if_stack_depth) {
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if_stack_array_size *= 2;
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if_stack = reralloc(mem_ctx, if_stack, int, if_stack_array_size);
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}
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}
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gen8_instruction *
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gen8_generator::pop_if_stack()
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{
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--if_stack_depth;
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return &store[if_stack[if_stack_depth]];
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}
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/**
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* Patch the IF and ELSE instructions to set the jump offsets (JIP and UIP.)
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*/
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void
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gen8_generator::patch_IF_ELSE(gen8_instruction *if_inst,
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gen8_instruction *else_inst,
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gen8_instruction *endif_inst)
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{
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assert(if_inst != NULL && gen8_opcode(if_inst) == BRW_OPCODE_IF);
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assert(else_inst == NULL || gen8_opcode(else_inst) == BRW_OPCODE_ELSE);
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assert(endif_inst != NULL && gen8_opcode(endif_inst) == BRW_OPCODE_ENDIF);
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gen8_set_exec_size(endif_inst, gen8_exec_size(if_inst));
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if (else_inst == NULL) {
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/* Patch IF -> ENDIF */
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gen8_set_jip(if_inst, 16 * (endif_inst - if_inst));
|
||||
gen8_set_uip(if_inst, 16 * (endif_inst - if_inst));
|
||||
} else {
|
||||
gen8_set_exec_size(else_inst, gen8_exec_size(if_inst));
|
||||
|
||||
/* Patch IF -> ELSE and ELSE -> ENDIF:
|
||||
*
|
||||
* The IF's JIP should point at the instruction after the ELSE.
|
||||
* The IF's UIP should point to the ENDIF.
|
||||
*
|
||||
* Both are expressed in bytes, hence the multiply by 16...128-bits.
|
||||
*/
|
||||
gen8_set_jip(if_inst, 16 * (else_inst - if_inst + 1));
|
||||
gen8_set_uip(if_inst, 16 * (endif_inst - if_inst));
|
||||
|
||||
/* Patch ELSE -> ENDIF:
|
||||
*
|
||||
* Since we don't set branch_ctrl, both JIP and UIP point to ENDIF.
|
||||
*/
|
||||
gen8_set_jip(else_inst, 16 * (endif_inst - else_inst));
|
||||
gen8_set_uip(else_inst, 16 * (endif_inst - else_inst));
|
||||
}
|
||||
gen8_set_jip(endif_inst, 16);
|
||||
}
|
||||
|
||||
gen8_instruction *
|
||||
gen8_generator::IF(unsigned predicate)
|
||||
{
|
||||
gen8_instruction *inst = next_inst(BRW_OPCODE_IF);
|
||||
gen8_set_dst(brw, inst, vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_D)));
|
||||
gen8_set_exec_size(inst, default_state.exec_size);
|
||||
gen8_set_pred_control(inst, predicate);
|
||||
gen8_set_mask_control(inst, BRW_MASK_ENABLE);
|
||||
push_if_stack(inst);
|
||||
|
||||
return inst;
|
||||
}
|
||||
|
||||
gen8_instruction *
|
||||
gen8_generator::ELSE()
|
||||
{
|
||||
gen8_instruction *inst = next_inst(BRW_OPCODE_ELSE);
|
||||
gen8_set_dst(brw, inst, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
|
||||
gen8_set_mask_control(inst, BRW_MASK_ENABLE);
|
||||
push_if_stack(inst);
|
||||
return inst;
|
||||
}
|
||||
|
||||
gen8_instruction *
|
||||
gen8_generator::ENDIF()
|
||||
{
|
||||
gen8_instruction *if_inst = NULL;
|
||||
gen8_instruction *else_inst = NULL;
|
||||
|
||||
gen8_instruction *tmp = pop_if_stack();
|
||||
if (gen8_opcode(tmp) == BRW_OPCODE_ELSE) {
|
||||
else_inst = tmp;
|
||||
tmp = pop_if_stack();
|
||||
}
|
||||
assert(gen8_opcode(tmp) == BRW_OPCODE_IF);
|
||||
if_inst = tmp;
|
||||
|
||||
gen8_instruction *endif_inst = next_inst(BRW_OPCODE_ENDIF);
|
||||
gen8_set_mask_control(endif_inst, BRW_MASK_ENABLE);
|
||||
patch_IF_ELSE(if_inst, else_inst, endif_inst);
|
||||
|
||||
return endif_inst;
|
||||
}
|
||||
|
||||
unsigned
|
||||
gen8_generator::next_ip(unsigned ip) const
|
||||
{
|
||||
return ip + 16;
|
||||
}
|
||||
|
||||
unsigned
|
||||
gen8_generator::find_next_block_end(unsigned start) const
|
||||
{
|
||||
for (unsigned ip = next_ip(start); ip < next_inst_offset; ip = next_ip(ip)) {
|
||||
gen8_instruction *inst = &store[ip / 16];
|
||||
|
||||
switch (gen8_opcode(inst)) {
|
||||
case BRW_OPCODE_ENDIF:
|
||||
case BRW_OPCODE_ELSE:
|
||||
case BRW_OPCODE_WHILE:
|
||||
case BRW_OPCODE_HALT:
|
||||
return ip;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* There is no DO instruction on Gen6+, so to find the end of the loop
|
||||
* we have to see if the loop is jumping back before our start
|
||||
* instruction.
|
||||
*/
|
||||
unsigned
|
||||
gen8_generator::find_loop_end(unsigned start) const
|
||||
{
|
||||
/* Always start after the instruction (such as a WHILE) we're trying to fix
|
||||
* up.
|
||||
*/
|
||||
for (unsigned ip = next_ip(start); ip < next_inst_offset; ip = next_ip(ip)) {
|
||||
gen8_instruction *inst = &store[ip / 16];
|
||||
|
||||
if (gen8_opcode(inst) == BRW_OPCODE_WHILE) {
|
||||
if (ip + gen8_jip(inst) <= start)
|
||||
return ip;
|
||||
}
|
||||
}
|
||||
assert(!"not reached");
|
||||
return start;
|
||||
}
|
||||
|
||||
/* After program generation, go back and update the UIP and JIP of
|
||||
* BREAK, CONT, and HALT instructions to their correct locations.
|
||||
*/
|
||||
void
|
||||
gen8_generator::patch_jump_targets()
|
||||
{
|
||||
for (unsigned ip = 0; ip < next_inst_offset; ip = next_ip(ip)) {
|
||||
gen8_instruction *inst = &store[ip / 16];
|
||||
|
||||
int block_end_ip = find_next_block_end(ip);
|
||||
switch (gen8_opcode(inst)) {
|
||||
case BRW_OPCODE_BREAK:
|
||||
assert(block_end_ip != 0);
|
||||
gen8_set_jip(inst, block_end_ip - ip);
|
||||
gen8_set_uip(inst, find_loop_end(ip) - ip);
|
||||
assert(gen8_uip(inst) != 0);
|
||||
assert(gen8_jip(inst) != 0);
|
||||
break;
|
||||
case BRW_OPCODE_CONTINUE:
|
||||
assert(block_end_ip != 0);
|
||||
gen8_set_jip(inst, block_end_ip - ip);
|
||||
gen8_set_uip(inst, find_loop_end(ip) - ip);
|
||||
assert(gen8_uip(inst) != 0);
|
||||
assert(gen8_jip(inst) != 0);
|
||||
break;
|
||||
case BRW_OPCODE_ENDIF:
|
||||
if (block_end_ip == 0)
|
||||
gen8_set_jip(inst, 16);
|
||||
else
|
||||
gen8_set_jip(inst, block_end_ip - ip);
|
||||
break;
|
||||
case BRW_OPCODE_HALT:
|
||||
/* From the Sandy Bridge PRM (volume 4, part 2, section 8.3.19):
|
||||
*
|
||||
* "In case of the halt instruction not inside any conditional
|
||||
* code block, the value of <JIP> and <UIP> should be the
|
||||
* same. In case of the halt instruction inside conditional code
|
||||
* block, the <UIP> should be the end of the program, and the
|
||||
* <JIP> should be end of the most inner conditional code block."
|
||||
*
|
||||
* The uip will have already been set by whoever set up the
|
||||
* instruction.
|
||||
*/
|
||||
if (block_end_ip == 0) {
|
||||
gen8_set_jip(inst, gen8_uip(inst));
|
||||
} else {
|
||||
gen8_set_jip(inst, block_end_ip - ip);
|
||||
}
|
||||
assert(gen8_uip(inst) != 0);
|
||||
assert(gen8_jip(inst) != 0);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
gen8_generator::DO()
|
||||
{
|
||||
if (loop_stack_array_size < loop_stack_depth) {
|
||||
loop_stack_array_size *= 2;
|
||||
loop_stack = reralloc(mem_ctx, loop_stack, int, loop_stack_array_size);
|
||||
}
|
||||
loop_stack[loop_stack_depth++] = nr_inst;
|
||||
}
|
||||
|
||||
gen8_instruction *
|
||||
gen8_generator::BREAK()
|
||||
{
|
||||
gen8_instruction *inst = next_inst(BRW_OPCODE_BREAK);
|
||||
gen8_set_dst(brw, inst, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
|
||||
gen8_set_src0(brw, inst, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
|
||||
gen8_set_src1(brw, inst, brw_imm_d(0));
|
||||
gen8_set_exec_size(inst, default_state.exec_size);
|
||||
return inst;
|
||||
}
|
||||
|
||||
gen8_instruction *
|
||||
gen8_generator::CONTINUE()
|
||||
{
|
||||
gen8_instruction *inst = next_inst(BRW_OPCODE_CONTINUE);
|
||||
gen8_set_dst(brw, inst, brw_ip_reg());
|
||||
gen8_set_src0(brw, inst, brw_ip_reg());
|
||||
gen8_set_src1(brw, inst, brw_imm_d(0));
|
||||
gen8_set_exec_size(inst, default_state.exec_size);
|
||||
return inst;
|
||||
}
|
||||
|
||||
gen8_instruction *
|
||||
gen8_generator::WHILE()
|
||||
{
|
||||
gen8_instruction *do_inst = &store[loop_stack[--loop_stack_depth]];
|
||||
gen8_instruction *while_inst = next_inst(BRW_OPCODE_WHILE);
|
||||
|
||||
gen8_set_dst(brw, while_inst, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
|
||||
gen8_set_src0(brw, while_inst, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
|
||||
gen8_set_src1(brw, while_inst, brw_imm_ud(0));
|
||||
gen8_set_jip(while_inst, 16 * (do_inst - while_inst));
|
||||
gen8_set_exec_size(while_inst, default_state.exec_size);
|
||||
|
||||
return while_inst;
|
||||
}
|
||||
|
||||
gen8_instruction *
|
||||
gen8_generator::HALT()
|
||||
{
|
||||
gen8_instruction *inst = next_inst(BRW_OPCODE_HALT);
|
||||
gen8_set_dst(brw, inst, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
|
||||
gen8_set_src0(brw, inst, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
|
||||
gen8_set_exec_size(inst, default_state.exec_size);
|
||||
gen8_set_mask_control(inst, BRW_MASK_DISABLE);
|
||||
return inst;
|
||||
}
|
||||
|
||||
void
|
||||
gen8_generator::disassemble(FILE *out, int start, int end)
|
||||
{
|
||||
bool dump_hex = false;
|
||||
|
||||
for (int offset = start; offset < end; offset += 16) {
|
||||
gen8_instruction *inst = &store[offset / 16];
|
||||
printf("0x%08x: ", offset);
|
||||
|
||||
if (dump_hex) {
|
||||
printf("0x%08x 0x%08x 0x%08x 0x%08x ",
|
||||
((uint32_t *) inst)[3],
|
||||
((uint32_t *) inst)[2],
|
||||
((uint32_t *) inst)[1],
|
||||
((uint32_t *) inst)[0]);
|
||||
}
|
||||
|
||||
gen8_disassemble(stdout, inst, brw->gen);
|
||||
}
|
||||
}
|
||||
198
src/mesa/drivers/dri/i965/gen8_generator.h
Normal file
198
src/mesa/drivers/dri/i965/gen8_generator.h
Normal file
|
|
@ -0,0 +1,198 @@
|
|||
/*
|
||||
* Copyright © 2012 Intel Corporation
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
|
||||
* IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file gen8_generator.h
|
||||
*
|
||||
* Code generation for Gen8+ hardware, replacing the brw_eu_emit.c layer.
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
extern "C" {
|
||||
#include "main/macros.h"
|
||||
} /* extern "C" */
|
||||
|
||||
#include "gen8_instruction.h"
|
||||
|
||||
class gen8_generator {
|
||||
public:
|
||||
gen8_generator(struct brw_context *brw,
|
||||
struct gl_shader_program *shader_prog,
|
||||
struct gl_program *prog,
|
||||
void *mem_ctx);
|
||||
~gen8_generator();
|
||||
|
||||
/**
|
||||
* Instruction emitters.
|
||||
* @{
|
||||
*/
|
||||
#define ALU1(OP) \
|
||||
gen8_instruction *OP(struct brw_reg dst, struct brw_reg src);
|
||||
#define ALU2(OP) \
|
||||
gen8_instruction *OP(struct brw_reg d, struct brw_reg, struct brw_reg);
|
||||
#define ALU3(OP) \
|
||||
gen8_instruction *OP(struct brw_reg d, \
|
||||
struct brw_reg, struct brw_reg, struct brw_reg);
|
||||
ALU2(ADD)
|
||||
ALU2(AND)
|
||||
ALU2(ASR)
|
||||
ALU3(BFE)
|
||||
ALU2(BFI1)
|
||||
ALU3(BFI2)
|
||||
ALU1(F32TO16)
|
||||
ALU1(F16TO32)
|
||||
ALU1(BFREV)
|
||||
ALU1(CBIT)
|
||||
ALU2(ADDC)
|
||||
ALU2(SUBB)
|
||||
ALU2(DP2)
|
||||
ALU2(DP3)
|
||||
ALU2(DP4)
|
||||
ALU2(DPH)
|
||||
ALU1(FBH)
|
||||
ALU1(FBL)
|
||||
ALU1(FRC)
|
||||
ALU2(LINE)
|
||||
ALU3(LRP)
|
||||
ALU2(MAC)
|
||||
ALU2(MACH)
|
||||
ALU3(MAD)
|
||||
ALU2(MUL)
|
||||
ALU1(MOV)
|
||||
ALU1(MOV_RAW)
|
||||
ALU1(NOT)
|
||||
ALU2(OR)
|
||||
ALU2(PLN)
|
||||
ALU1(RNDD)
|
||||
ALU1(RNDE)
|
||||
ALU1(RNDZ)
|
||||
ALU2(SEL)
|
||||
ALU2(SHL)
|
||||
ALU2(SHR)
|
||||
ALU2(XOR)
|
||||
#undef ALU1
|
||||
#undef ALU2
|
||||
#undef ALU3
|
||||
|
||||
gen8_instruction *CMP(struct brw_reg dst, unsigned conditional,
|
||||
struct brw_reg src0, struct brw_reg src1);
|
||||
gen8_instruction *IF(unsigned predicate);
|
||||
gen8_instruction *ELSE();
|
||||
gen8_instruction *ENDIF();
|
||||
void DO();
|
||||
gen8_instruction *BREAK();
|
||||
gen8_instruction *CONTINUE();
|
||||
gen8_instruction *WHILE();
|
||||
|
||||
gen8_instruction *HALT();
|
||||
|
||||
gen8_instruction *MATH(unsigned math_function,
|
||||
struct brw_reg dst,
|
||||
struct brw_reg src0);
|
||||
gen8_instruction *MATH(unsigned math_function,
|
||||
struct brw_reg dst,
|
||||
struct brw_reg src0,
|
||||
struct brw_reg src1);
|
||||
gen8_instruction *NOP();
|
||||
/** @} */
|
||||
|
||||
void disassemble(FILE *out, int start, int end);
|
||||
|
||||
protected:
|
||||
gen8_instruction *alu3(unsigned opcode,
|
||||
struct brw_reg dst,
|
||||
struct brw_reg src0,
|
||||
struct brw_reg src1,
|
||||
struct brw_reg src2);
|
||||
|
||||
gen8_instruction *math(unsigned math_function,
|
||||
struct brw_reg dst,
|
||||
struct brw_reg src0);
|
||||
|
||||
gen8_instruction *next_inst(unsigned opcode);
|
||||
|
||||
struct gl_shader_program *shader_prog;
|
||||
struct gl_shader *shader;
|
||||
struct gl_program *prog;
|
||||
|
||||
struct brw_context *brw;
|
||||
struct intel_context *intel;
|
||||
struct gl_context *ctx;
|
||||
|
||||
gen8_instruction *store;
|
||||
unsigned store_size;
|
||||
unsigned nr_inst;
|
||||
unsigned next_inst_offset;
|
||||
|
||||
/**
|
||||
* Control flow stacks:
|
||||
*
|
||||
* if_stack contains IF and ELSE instructions which must be patched with
|
||||
* the final jump offsets (and popped) once the matching ENDIF is encountered.
|
||||
*
|
||||
* We actually store an array index into the store, rather than pointers
|
||||
* to the instructions. This is necessary since we may realloc the store.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
int *if_stack;
|
||||
int if_stack_depth;
|
||||
int if_stack_array_size;
|
||||
|
||||
int *loop_stack;
|
||||
int loop_stack_depth;
|
||||
int loop_stack_array_size;
|
||||
|
||||
int if_depth_in_loop;
|
||||
|
||||
void push_if_stack(gen8_instruction *inst);
|
||||
gen8_instruction *pop_if_stack();
|
||||
/** @} */
|
||||
|
||||
void patch_IF_ELSE(gen8_instruction *if_inst,
|
||||
gen8_instruction *else_inst,
|
||||
gen8_instruction *endif_inst);
|
||||
|
||||
unsigned next_ip(unsigned ip) const;
|
||||
unsigned find_next_block_end(unsigned start_ip) const;
|
||||
unsigned find_loop_end(unsigned start) const;
|
||||
|
||||
void patch_jump_targets();
|
||||
|
||||
/**
|
||||
* Default state for new instructions.
|
||||
*/
|
||||
struct {
|
||||
unsigned exec_size;
|
||||
unsigned access_mode;
|
||||
unsigned mask_control;
|
||||
unsigned flag_subreg_nr;
|
||||
unsigned conditional_mod;
|
||||
unsigned predicate;
|
||||
bool predicate_inverse;
|
||||
bool saturate;
|
||||
} default_state;
|
||||
|
||||
void *mem_ctx;
|
||||
};
|
||||
Loading…
Add table
Reference in a new issue