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intel/elk: Remove dead TXL_LZ/TXF_LZ opcodes
These opcodes were only emitted for Gen9+ hardware, but elk only targets Gen8 and below. Fixes:05d78994a7("intel/elk: Remove Gfx9+ sampler messages and modes") (cherry picked from commitd36a578bc0) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41269>
This commit is contained in:
parent
e1733d1b38
commit
f776afb2db
8 changed files with 3 additions and 24 deletions
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@ -4574,7 +4574,7 @@
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"description": "intel/elk: Remove dead TXL_LZ/TXF_LZ opcodes",
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"nominated": true,
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"nomination_type": 2,
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"resolution": 0,
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"resolution": 1,
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"main_sha": null,
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"because_sha": "05d78994a763d220f69cb9770fcc6c4e9cb40275",
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"notes": null
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@ -145,10 +145,8 @@ enum elk_opcode {
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ELK_SHADER_OPCODE_TXD_LOGICAL,
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ELK_SHADER_OPCODE_TXF,
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ELK_SHADER_OPCODE_TXF_LOGICAL,
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ELK_SHADER_OPCODE_TXF_LZ,
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ELK_SHADER_OPCODE_TXL,
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ELK_SHADER_OPCODE_TXL_LOGICAL,
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ELK_SHADER_OPCODE_TXL_LZ,
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ELK_SHADER_OPCODE_TXS,
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ELK_SHADER_OPCODE_TXS_LOGICAL,
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ELK_FS_OPCODE_TXB,
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@ -265,13 +265,11 @@ elk_fs_inst::is_control_source(unsigned arg) const
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case ELK_FS_OPCODE_TXB:
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case ELK_SHADER_OPCODE_TXD:
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case ELK_SHADER_OPCODE_TXF:
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case ELK_SHADER_OPCODE_TXF_LZ:
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case ELK_SHADER_OPCODE_TXF_CMS:
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case ELK_SHADER_OPCODE_TXF_CMS_W:
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case ELK_SHADER_OPCODE_TXF_UMS:
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case ELK_SHADER_OPCODE_TXF_MCS:
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case ELK_SHADER_OPCODE_TXL:
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case ELK_SHADER_OPCODE_TXL_LZ:
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case ELK_SHADER_OPCODE_TXS:
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case ELK_SHADER_OPCODE_LOD:
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case ELK_SHADER_OPCODE_TG4:
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@ -305,13 +303,11 @@ elk_fs_inst::is_payload(unsigned arg) const
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case ELK_FS_OPCODE_TXB:
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case ELK_SHADER_OPCODE_TXD:
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case ELK_SHADER_OPCODE_TXF:
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case ELK_SHADER_OPCODE_TXF_LZ:
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case ELK_SHADER_OPCODE_TXF_CMS:
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case ELK_SHADER_OPCODE_TXF_CMS_W:
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case ELK_SHADER_OPCODE_TXF_UMS:
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case ELK_SHADER_OPCODE_TXF_MCS:
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case ELK_SHADER_OPCODE_TXL:
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case ELK_SHADER_OPCODE_TXL_LZ:
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case ELK_SHADER_OPCODE_TXS:
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case ELK_SHADER_OPCODE_LOD:
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case ELK_SHADER_OPCODE_TG4:
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@ -878,13 +874,11 @@ elk_fs_inst::size_read(int arg) const
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case ELK_FS_OPCODE_TXB:
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case ELK_SHADER_OPCODE_TXD:
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case ELK_SHADER_OPCODE_TXF:
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case ELK_SHADER_OPCODE_TXF_LZ:
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case ELK_SHADER_OPCODE_TXF_CMS:
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case ELK_SHADER_OPCODE_TXF_CMS_W:
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case ELK_SHADER_OPCODE_TXF_UMS:
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case ELK_SHADER_OPCODE_TXF_MCS:
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case ELK_SHADER_OPCODE_TXL:
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case ELK_SHADER_OPCODE_TXL_LZ:
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case ELK_SHADER_OPCODE_TXS:
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case ELK_SHADER_OPCODE_LOD:
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case ELK_SHADER_OPCODE_TG4:
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@ -830,9 +830,7 @@ namespace {
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case ELK_FS_OPCODE_TXB:
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case ELK_SHADER_OPCODE_TXD:
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case ELK_SHADER_OPCODE_TXF:
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case ELK_SHADER_OPCODE_TXF_LZ:
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case ELK_SHADER_OPCODE_TXL:
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case ELK_SHADER_OPCODE_TXL_LZ:
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case ELK_SHADER_OPCODE_TXF_CMS:
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case ELK_SHADER_OPCODE_TXF_CMS_W:
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case ELK_SHADER_OPCODE_TXF_UMS:
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@ -847,15 +847,12 @@ lower_sampler_logical_send_gfx7(const fs_builder &bld, elk_fs_inst *inst, elk_op
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bld.MOV(sources[length++], elk_imm_ud(0));
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break;
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case ELK_SHADER_OPCODE_TXF:
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case ELK_SHADER_OPCODE_TXF_LZ:
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/* Unfortunately, the parameters for LD are intermixed: u, lod, v, r. */
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sources[length] = retype(sources[length], payload_signed_type);
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bld.MOV(sources[length++], coordinate);
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if (op != ELK_SHADER_OPCODE_TXF_LZ) {
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sources[length] = retype(sources[length], payload_signed_type);
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bld.MOV(sources[length++], lod);
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}
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sources[length] = retype(sources[length], payload_signed_type);
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bld.MOV(sources[length++], lod);
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for (unsigned i = 1; i < coord_components; i++) {
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sources[length] = retype(sources[length], payload_signed_type);
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@ -278,9 +278,7 @@ elk_schedule_node::set_latency_gfx7(const struct elk_isa_info *isa)
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case ELK_SHADER_OPCODE_TEX:
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case ELK_SHADER_OPCODE_TXD:
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case ELK_SHADER_OPCODE_TXF:
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case ELK_SHADER_OPCODE_TXF_LZ:
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case ELK_SHADER_OPCODE_TXL:
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case ELK_SHADER_OPCODE_TXL_LZ:
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/* 18 cycles:
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* mov(8) g115<1>F 0F { align1 WE_normal 1Q };
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* mov(8) g114<1>F 0F { align1 WE_normal 1Q };
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@ -216,14 +216,10 @@ elk_instruction_name(const struct elk_isa_info *isa, enum elk_opcode op)
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return "txf";
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case ELK_SHADER_OPCODE_TXF_LOGICAL:
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return "txf_logical";
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case ELK_SHADER_OPCODE_TXF_LZ:
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return "txf_lz";
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case ELK_SHADER_OPCODE_TXL:
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return "txl";
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case ELK_SHADER_OPCODE_TXL_LOGICAL:
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return "txl_logical";
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case ELK_SHADER_OPCODE_TXL_LZ:
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return "txl_lz";
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case ELK_SHADER_OPCODE_TXS:
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return "txs";
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case ELK_SHADER_OPCODE_TXS_LOGICAL:
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@ -294,13 +294,11 @@ vec4_instruction::can_do_writemask(const struct intel_device_info *devinfo)
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case ELK_FS_OPCODE_TXB:
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case ELK_SHADER_OPCODE_TXD:
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case ELK_SHADER_OPCODE_TXF:
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case ELK_SHADER_OPCODE_TXF_LZ:
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case ELK_SHADER_OPCODE_TXF_CMS:
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case ELK_SHADER_OPCODE_TXF_CMS_W:
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case ELK_SHADER_OPCODE_TXF_UMS:
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case ELK_SHADER_OPCODE_TXF_MCS:
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case ELK_SHADER_OPCODE_TXL:
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case ELK_SHADER_OPCODE_TXL_LZ:
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case ELK_SHADER_OPCODE_TXS:
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case ELK_SHADER_OPCODE_LOD:
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case ELK_SHADER_OPCODE_TG4:
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