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intel/compiler: move gen5 final pass to actually be final pass

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This got broken by the register conversion, this pass needs to be
after all the others.

Fixes: ce75c3c3fe ("intel: Switch to intrinsic-based registers")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26731>
This commit is contained in:
Dave Airlie 2023-12-18 16:47:56 +10:00 • committed by Marge Bot
parent 299cd1af82
commit f76f4be301
1 changed files with 9 additions and 8 deletions
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17
src/intel/compiler/brw_nir.c
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@ -1757,14 +1757,6 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
if (OPT(nir_opt_rematerialize_compares)) if (OPT(nir_opt_rematerialize_compares))
OPT(nir_opt_dce); OPT(nir_opt_dce);
/* This is the last pass we run before we start emitting stuff. It
* determines when we need to insert boolean resolves on Gen <= 5. We
* run it last because it stashes data in instr->pass_flags and we don't
* want that to be squashed by other NIR passes.
*/
if (devinfo->ver <= 5)
brw_nir_analyze_boolean_resolves(nir);
OPT(nir_opt_dce); OPT(nir_opt_dce);
/* The mesh stages require this pass to be called at the last minute, /* The mesh stages require this pass to be called at the last minute,
@ -1777,6 +1769,15 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
brw_nir_adjust_payload(nir); brw_nir_adjust_payload(nir);
nir_trivialize_registers(nir); nir_trivialize_registers(nir);
/* This is the last pass we run before we start emitting stuff. It
* determines when we need to insert boolean resolves on Gen <= 5. We
* run it last because it stashes data in instr->pass_flags and we don't
* want that to be squashed by other NIR passes.
*/
if (devinfo->ver <= 5)
brw_nir_analyze_boolean_resolves(nir);
nir_sweep(nir); nir_sweep(nir);
if (unlikely(debug_enabled)) { if (unlikely(debug_enabled)) {