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intel: Switch to intrinsic-based registers

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Results on HSW (vec4 only):

    total instructions in shared programs: 2978400 -> 2974135 (-0.14%)
    instructions in affected programs: 77870 -> 73605 (-5.48%)
    helped: 143
    HURT: 48
    helped stats (abs) min: 1 max: 100 x̄: 30.22 x̃: 9
    helped stats (rel) min: 0.03% max: 30.49% x̄: 8.02% x̃: 6.39%
    HURT stats (abs)   min: 1 max: 4 x̄: 1.19 x̃: 1
    HURT stats (rel)   min: 0.08% max: 16.67% x̄: 3.71% x̃: 3.23%
    95% mean confidence interval for instructions value: -26.69 -17.97
    95% mean confidence interval for instructions %-change: -6.24% -3.90%
    Instructions are helped.

    total cycles in shared programs: 45345924 -> 44742666 (-1.33%)
    cycles in affected programs: 29083466 -> 28480208 (-2.07%)
    helped: 4785
    HURT: 3879
    helped stats (abs) min: 2 max: 8072 x̄: 276.00 x̃: 24
    helped stats (rel) min: 0.02% max: 54.43% x̄: 7.78% x̃: 1.95%
    HURT stats (abs)   min: 2 max: 14736 x̄: 184.95 x̃: 20
    HURT stats (rel)   min: 0.02% max: 97.00% x̄: 7.69% x̃: 1.53%
    95% mean confidence interval for cycles value: -83.49 -55.77
    95% mean confidence interval for cycles %-change: -1.16% -0.55%
    Cycles are helped.

    total spills in shared programs: 1093 -> 539 (-50.69%)
    spills in affected programs: 772 -> 218 (-71.76%)
    helped: 74
    HURT: 0

    total fills in shared programs: 760 -> 757 (-0.39%)
    fills in affected programs: 66 -> 63 (-4.55%)
    helped: 3
    HURT: 0

Results on TGL (all stages):

    total instructions in shared programs: 21486982 -> 21488266 (<.01%)
    instructions in affected programs: 2245938 -> 2247222 (0.06%)
    helped: 1288
    HURT: 1385
    helped stats (abs) min: 1 max: 93 x̄: 4.05 x̃: 2
    helped stats (rel) min: 0.02% max: 3.82% x̄: 0.61% x̃: 0.46%
    HURT stats (abs)   min: 1 max: 134 x̄: 4.69 x̃: 2
    HURT stats (rel)   min: <.01% max: 5.59% x̄: 0.65% x̃: 0.44%
    95% mean confidence interval for instructions value: 0.13 0.83
    95% mean confidence interval for instructions %-change: <.01% 0.08%
    Instructions are HURT.

    total cycles in shared programs: 809326677 -> 809475669 (0.02%)
    cycles in affected programs: 447781659 -> 447930651 (0.03%)
    helped: 1924
    HURT: 1994
    helped stats (abs) min: 1 max: 74567 x̄: 1217.49 x̃: 10
    helped stats (rel) min: <.01% max: 38.44% x̄: 1.09% x̃: 0.17%
    HURT stats (abs)   min: 1 max: 76426 x̄: 1249.47 x̃: 8
    HURT stats (rel)   min: <.01% max: 137.11% x̄: 1.64% x̃: 0.17%
    95% mean confidence interval for cycles value: -125.61 201.67
    95% mean confidence interval for cycles %-change: 0.12% 0.48%
    Inconclusive result (value mean confidence interval includes 0).

    LOST:   4
    GAINED: 4

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24104>
This commit is contained in:
Faith Ekstrand 2023-05-18 14:14:18 -05:00 • committed by Marge Bot
parent abb6188a04
commit ce75c3c3fe
3 changed files with 6 additions and 5 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/gallium/drivers/zink/ci/traces-zink.yml
View file

@ -35,7 +35,7 @@ traces:
checksum: 433b69bea68cfe81914b857bbdc60ea5
gputest/pixmark-piano-v2.trace:
gl-zink-anv-tgl:
checksum: 897c704551c305c1cfb7cc6293cd495d
checksum: 096ff1ec0d3bec4e70ff6d23baabb795
gputest/triangle-v2.trace:
gl-zink-anv-tgl:
checksum: 5f694874b15bcd7a3689b387c143590b

1
src/intel/compiler/brw_fs_nir.cpp
View file

@ -4364,7 +4364,6 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
/* Re-use the destination's slot in the table for the register */
nir_ssa_values[instr->dest.ssa.index] =
bld.vgrf(reg_type, num_components);
bld.UNDEF(nir_ssa_values[instr->dest.ssa.index]);
return;
}

8
src/intel/compiler/brw_nir.c
View file

@ -1706,7 +1706,7 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
OPT(nir_copy_prop);
OPT(nir_opt_dce);
OPT(nir_lower_locals_to_regs, 32);
OPT(nir_lower_locals_to_reg_intrinsics, 32);
if (unlikely(debug_enabled)) {
/* Re-index SSA defs so we print more sensible numbers. */
@ -1721,11 +1721,11 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
nir_validate_ssa_dominance(nir, "before nir_convert_from_ssa");
OPT(nir_convert_from_ssa, true, false);
OPT(nir_convert_from_ssa, true, true);
if (!is_scalar) {
OPT(nir_move_vec_src_uses_to_dest);
OPT(nir_lower_vec_to_movs, NULL, NULL);
OPT(nir_lower_vec_to_regs, NULL, NULL);
}
OPT(nir_opt_dce);
@ -1741,6 +1741,8 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
if (devinfo->ver <= 5)
brw_nir_analyze_boolean_resolves(nir);
OPT(nir_opt_dce);
nir_trivialize_registers(nir);
nir_sweep(nir);
if (unlikely(debug_enabled)) {