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intel/isl: Add more PRM text for HiZ/STC requirement

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Add text describing why HierarchicalDepthBufferEnable must be set along
with SeparateStencilBufferEnable.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14825>
This commit is contained in:
Nanley Chery 2022-02-01 14:02:16 -05:00 • committed by Marge Bot
parent bc9ce9705c
commit f724f95542
1 changed files with 8 additions and 5 deletions
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13
src/intel/isl/isl_emit_depth_stencil.c
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@ -152,14 +152,17 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
info->stencil_surf && info->stencil_surf->format == ISL_FORMAT_R8_UINT;
if (separate_stencil || info->hiz_usage == ISL_AUX_USAGE_HIZ) {
assert(ISL_DEV_USE_SEPARATE_STENCIL(dev));
db.SeparateStencilBufferEnable = true;
db.HierarchicalDepthBufferEnable = true;
/* From the IronLake PRM, Vol 2 Part 1,
* 3DSTATE_DEPTH_BUFFER::Tiled Surface,
/* From the IronLake PRM, Vol 2 Part 1:
*
* 3DSTATE_DEPTH_BUFFER::Separate Stencil Buffer Enable
* If this field is enabled, Hierarchical Depth Buffer Enable must
* also be enabled.
*
* 3DSTATE_DEPTH_BUFFER::Tiled Surface
* When Hierarchical Depth Buffer is enabled, this bit must be set.
*/
db.SeparateStencilBufferEnable = true;
db.HierarchicalDepthBufferEnable = true;
db.TiledSurface = true;
}
#endif