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freedreno/registers: Fix gen8 TPL1_MODE_CNTL

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Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39167>
This commit is contained in:
Rob Clark 2026-01-08 09:43:35 -08:00 • committed by Marge Bot
parent ff034b5aef
commit f5f9fecfc3
3 changed files with 12 additions and 5 deletions
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9
src/freedreno/registers/adreno/a6xx.xml
View file

@ -4382,15 +4382,15 @@ by a particular renderpass/blit.
<enum name="a6xx_coord_round">
<value value="0" name="COORD_TRUNCATE"/>
<value value="1" name="COORD_ROUND_NEAREST_EVEN"/>
<value value="2" name="ROUND_FLOAT_TO_INT"/> <!-- only ARRAYCOORDROUNDMODE -->
</enum>
<enum name="a6xx_nearest_mode">
<value value="0" name="ROUND_CLAMP_TRUNCATE"/>
<value value="1" name="CLAMP_ROUND_TRUNCATE"/>
<value value="2" name="ROUND_FLOAT_TO_INT"/> <!-- only ARRAYCOORDROUNDMODE -->
</enum>
<reg32 offset="0xb309" name="TPL1_MODE_CNTL" usage="cmd">
<bitset name="a6xx_tpl1_mode_cntl" inline="yes">
<bitfield name="ISAMMODE" low="0" high="1" type="a6xx_isam_mode"/>
<bitfield name="TEXCOORDROUNDMODE" pos="2" type="a6xx_coord_round"/>
<bitfield name="ARRAYCOORDROUNDMODE" low="3" high="4" type="a6xx_coord_round"/>
@ -4398,6 +4398,11 @@ by a particular renderpass/blit.
<bitfield name="SAMPLEREPLICATE" pos="6" type="boolean"/>
<bitfield name="DESTDATATYPEOVERRIDE" pos="7" type="boolean"/>
<bitfield name="PACK_SAMP_REDUCED_PRECISION" pos="8" type="boolean"/>
</bitset>
<reg32 offset="0xb309" name="TPL1_MODE_CNTL" usage="cmd" type="a6xx_tpl1_mode_cntl" variants="A6XX-A7XX"/>
<reg32 offset="0xb309" name="TPL1_MODE_CNTL" usage="cmd" type="a6xx_tpl1_mode_cntl" variants="A8XX-">
<bitfield name="CLAMP_DISABLE" pos="12" type="boolean"/>
</reg32>
<reg32 offset="0xb310" name="SP_UNKNOWN_B310" variants="A7XX-" usage="cmd"/>

5
src/freedreno/vulkan/tu_cmd_buffer.cc
View file

@ -2119,12 +2119,13 @@ tu6_init_static_regs(struct tu_device *dev, struct tu_cs *cs)
}
tu_cs_emit_regs(cs, VPC_LB_MODE_CNTL(CHIP));
tu_cs_emit_regs(cs, PC_CONTEXT_SWITCH_GFX_PREEMPTION_MODE(CHIP));
tu_cs_emit_regs(cs, A6XX_TPL1_MODE_CNTL(.isammode = ISAMMODE_GL,
tu_cs_emit_regs(cs, TPL1_MODE_CNTL(CHIP, .isammode = ISAMMODE_GL,
.texcoordroundmode = dev->instance->use_tex_coord_round_nearest_even_mode
? COORD_ROUND_NEAREST_EVEN
: COORD_TRUNCATE,
.nearestmipsnap = CLAMP_ROUND_TRUNCATE,
.destdatatypeoverride = true));
.destdatatypeoverride = true,
.clamp_disable = true));
tu_cs_emit_regs(cs, SP_REG_PROG_ID_3(CHIP, .dword = 0xfc));
tu_cs_emit_write_reg(cs, REG_A6XX_VFD_RENDER_MODE, 0x00000000);

3
src/gallium/drivers/freedreno/a6xx/fd6_emit.cc
View file

@ -996,11 +996,12 @@ fd6_emit_static_context_regs(struct fd_context *ctx, fd_cs &cs)
crb.add(VPC_UNKNOWN_9210(CHIP));
}
crb.add(A6XX_TPL1_MODE_CNTL(
crb.add(TPL1_MODE_CNTL(CHIP,
.isammode = ISAMMODE_GL,
.texcoordroundmode = COORD_TRUNCATE,
.nearestmipsnap = CLAMP_ROUND_TRUNCATE,
.destdatatypeoverride = true,
.clamp_disable = true,
));
crb.add(SP_REG_PROG_ID_3(