freedreno/registers: Fix gen8 GRAS_SU_STEREO_CNTL

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39167>
This commit is contained in:
Rob Clark 2026-01-09 15:31:43 -08:00 committed by Marge Bot
parent a2dc77323d
commit ff034b5aef

View file

@ -1549,7 +1549,7 @@ by a particular renderpass/blit.
<reg32 offset="1" name="MAX" type="float"/>
</array>
<bitset name="a6xx_gras_su_cntl" varset="chip">
<bitset name="a6xx_gras_su_cntl" inline="yes">
<bitfield name="CULL_FRONT" pos="0" type="boolean"/>
<bitfield name="CULL_BACK" pos="1" type="boolean"/>
<bitfield name="FRONT_CW" pos="2" type="boolean"/>
@ -1569,17 +1569,18 @@ by a particular renderpass/blit.
TODO: what about gen2 (a640)?
-->
<bitfield name="MULTIVIEW_ENABLE" pos="17" type="boolean"/>
<bitfield name="RENDERTARGETINDEXINCR" pos="18" type="boolean" variants="A6XX-A7XX"/>
<bitfield name="VIEWPORTINDEXINCR" pos="19" type="boolean" variants="A6XX-A7XX"/>
<bitfield name="UNK20" low="20" high="22" variants="A6XX-A7XX"/>
</bitset>
<reg32 offset="0x8090" name="GRAS_SU_CNTL" type="a6xx_gras_su_cntl" variants="A6XX-A7XX" usage="rp_blit"/>
<reg32 offset="0x8090" name="GRAS_SU_CNTL" type="a6xx_gras_su_cntl" variants="A6XX-A7XX" usage="rp_blit">
<bitfield name="RENDERTARGETINDEXINCR" pos="18" type="boolean"/>
<bitfield name="VIEWPORTINDEXINCR" pos="19" type="boolean"/>
<bitfield name="UNK20" low="20" high="22"/>
</reg32>
<reg32 offset="0x8209" name="GRAS_SU_CNTL" type="a6xx_gras_su_cntl" variants="A8XX-" usage="rp_blit"/>
<!-- Fields moved from GRAS_SU_CNTL on earlier gens: -->
<reg32 offset="0x820c" name="GRAS_SU_STEREO_CNTL" variants="A8XX-" usage="rp_blit">
<bitfield name="RENDERTARGETINDEXINCR" pos="18" type="boolean"/>
<bitfield name="VIEWPORTINDEXINCR" pos="19" type="boolean"/>
<bitfield name="RENDERTARGETINDEXINCR" pos="0" type="boolean"/>
<bitfield name="VIEWPORTINDEXINCR" pos="1" type="boolean"/>
</reg32>
<bitset name="a6xx_gras_su_point_minmax" inline="yes">