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radeonsi: move PA_SU_SC_MODE_CNTL to rasterizer state

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This requires enabling the optional GL provoking vertex behavior for quads.

+ some cosmetic changes, so that the register is set exactly the same as
on r600.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
This commit is contained in:
Marek Olšák 2015-03-15 18:53:50 +01:00
parent 98a2398222
commit f5832f3f9d
5 changed files with 14 additions and 30 deletions
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2
src/gallium/drivers/radeonsi/si_pipe.c
View file

@ -233,6 +233,7 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
case PIPE_CAP_POLYGON_OFFSET_CLAMP:
case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
return 1;
case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
@ -267,7 +268,6 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
case PIPE_CAP_VERTEX_COLOR_CLAMPED:
case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
case PIPE_CAP_USER_VERTEX_BUFFERS:
case PIPE_CAP_TGSI_TEXCOORD:
case PIPE_CAP_FAKE_SW_MSAA:

3
src/gallium/drivers/radeonsi/si_pipe.h
View file

@ -47,7 +47,7 @@
#define SI_TRACE_CS_DWORDS 6
#define SI_MAX_DRAW_CS_DWORDS \
(/*derived prim state:*/ 6 + /*draw regs:*/ 16 + /*draw packets:*/ 31)
(/*derived prim state:*/ 3 + /*draw regs:*/ 16 + /*draw packets:*/ 31)
/* Instruction cache. */
#define SI_CONTEXT_INV_ICACHE (R600_CONTEXT_PRIVATE_FLAG << 0)
@ -163,7 +163,6 @@ struct si_context {
struct si_framebuffer framebuffer;
struct si_vertex_element *vertex_elements;
unsigned pa_sc_line_stipple;
unsigned pa_su_sc_mode_cntl;
/* for saving when using blitter */
struct pipe_stencil_ref stencil_ref;
/* shaders */

32
src/gallium/drivers/radeonsi/si_state.c
View file

@ -605,7 +605,6 @@ static void *si_create_rs_state(struct pipe_context *ctx,
struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
struct si_pm4_state *pm4 = &rs->pm4;
unsigned tmp;
unsigned prov_vtx = 1, polygon_dual_mode;
float psize_min, psize_max;
if (rs == NULL) {
@ -620,28 +619,11 @@ static void *si_create_rs_state(struct pipe_context *ctx,
rs->line_smooth = state->line_smooth;
rs->poly_smooth = state->poly_smooth;
polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
state->fill_back != PIPE_POLYGON_MODE_FILL);
if (state->flatshade_first)
prov_vtx = 0;
rs->flatshade = state->flatshade;
rs->sprite_coord_enable = state->sprite_coord_enable;
rs->pa_sc_line_stipple = state->line_stipple_enable ?
S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
rs->pa_su_sc_mode_cntl =
S_028814_PROVOKING_VTX_LAST(prov_vtx) |
S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
S_028814_FACE(!state->front_ccw) |
S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
S_028814_POLY_MODE(polygon_dual_mode) |
S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back));
rs->pa_cl_clip_cntl =
S_028810_PS_UCP_MODE(3) |
S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
@ -698,7 +680,18 @@ static void *si_create_rs_state(struct pipe_context *ctx,
S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
S_028814_FACE(!state->front_ccw) |
S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
state->fill_back != PIPE_POLYGON_MODE_FILL) |
S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
return rs;
}
@ -714,7 +707,6 @@ static void si_bind_rs_state(struct pipe_context *ctx, void *state)
// TODO
sctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
sctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
if (sctx->framebuffer.nr_samples > 1 &&
(!old_rs || old_rs->multisample_enable != rs->multisample_enable))

1
src/gallium/drivers/radeonsi/si_state.h
View file

@ -62,7 +62,6 @@ struct si_state_rasterizer {
bool line_stipple_enable;
unsigned sprite_coord_enable;
unsigned pa_sc_line_stipple;
unsigned pa_su_sc_mode_cntl;
unsigned pa_cl_clip_cntl;
unsigned clip_plane_enable;
float offset_units;

6
src/gallium/drivers/radeonsi/si_state_draw.c
View file

@ -163,12 +163,6 @@ static void si_emit_rasterizer_prim_state(struct si_context *sctx)
S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 :
rast_prim == PIPE_PRIM_LINE_STRIP ? 2 : 0));
r600_write_context_reg(cs, R_028814_PA_SU_SC_MODE_CNTL,
sctx->pa_su_sc_mode_cntl |
S_028814_PROVOKING_VTX_LAST(rast_prim == PIPE_PRIM_QUADS ||
rast_prim == PIPE_PRIM_QUAD_STRIP ||
rast_prim == PIPE_PRIM_POLYGON));
sctx->last_rast_prim = rast_prim;
}