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nak: remove "reference which is immediately dereferenced by the compiler"

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Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38807>
This commit is contained in:
Eric Engestrom 2025-10-04 16:16:59 +02:00
parent 10396d8db6
commit f571428274
6 changed files with 11 additions and 11 deletions
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2
src/compiler/rust/proc/as_slice.rs
View file

@ -87,7 +87,7 @@ pub fn derive_as_slice(
if let Fields::Named(named) = s.fields {
for f in named.named {
let f_count = count_type(&f.ty, slice_type);
let f_attr = get_attr(&f, &attr_name);
let f_attr = get_attr(&f, attr_name);
if f_count > 0 {
assert!(

4
src/nouveau/compiler/nak/assign_regs.rs
View file

@ -685,7 +685,7 @@ impl<'a> VecRegAllocator<'a> {
if let Some(reg) = self.ra.try_find_unused_reg_range(0, comps, align, 0)
{
return self.assign_pin_vec_reg(&vec, reg);
return self.assign_pin_vec_reg(vec, reg);
}
let reg = self
@ -695,7 +695,7 @@ impl<'a> VecRegAllocator<'a> {
for c in 0..comps {
self.evict_reg_if_used(reg + u32::from(c));
}
self.assign_pin_vec_reg(&vec, reg)
self.assign_pin_vec_reg(vec, reg)
}
pub fn free_killed(&mut self, killed: &KillSet) {

4
src/nouveau/compiler/nak/calc_instr_deps.rs
View file

@ -542,7 +542,7 @@ impl TexQueueSimulationState {
// Push registers (if we are a tex instruction)
// We might need to insert a barrier if the queue is full
let push_level = if instr_needs_texbar(&instr) {
let push_level = if instr_needs_texbar(instr) {
let dst = instr.dsts()[0].as_reg().unwrap();
self.push(*dst)
} else {
@ -615,7 +615,7 @@ fn insert_texture_barriers(f: &mut Function, sm: &ShaderModelInfo) {
for instr in block.instrs.iter() {
// Ignore the barrier, we will recompute this later
let _bar = sim.visit_instr(&instr);
let _bar = sim.visit_instr(instr);
}
if *sim_out == sim {

2
src/nouveau/compiler/nak/sm20.rs
View file

@ -484,7 +484,7 @@ impl SM20Encoder<'_> {
self.set_opcode(unit, opcode);
self.set_dst(14..20, dst);
match AluSrc::from_src(Some(&src)) {
match AluSrc::from_src(Some(src)) {
AluSrc::None => panic!("src is always Some"),
AluSrc::Reg(reg) => {
self.set_reg(26..32, reg);

2
src/nouveau/compiler/nak/sm30_instr_latencies.rs
View file

@ -155,7 +155,7 @@ where
debug_assert!(bv.bits() == 8 * 7);
for (i, instr) in sched_chunk.iter().enumerate() {
encoder.encode_instr(&instr, &labels, &mut encoded);
encoder.encode_instr(instr, &labels, &mut encoded);
let sched = calc_instr_sched(prev_op, &instr.op, &instr.deps);
bv.set_field(i * 8..(i + 1) * 8, sched);

8
src/nouveau/compiler/nak/sm32.rs
View file

@ -642,7 +642,7 @@ impl SM32Op for OpRro {
}
SrcRef::CBuf(cb) => {
e.set_opcode(0x648, 2);
e.set_src_cbuf(23..42, &cb);
e.set_src_cbuf(23..42, cb);
}
_ => panic!("Invalid Rro src"),
}
@ -1087,7 +1087,7 @@ impl SM32Op for OpFlo {
}
SrcRef::CBuf(cb) => {
e.set_opcode(0x618, 2);
e.set_src_cbuf(23..42, &cb);
e.set_src_cbuf(23..42, cb);
}
_ => panic!("Invalid flo src"),
}
@ -2387,7 +2387,7 @@ impl SM32Op for OpSuLdGa {
e.set_mem_type(56..59, self.mem_type);
e.set_ld_cache_op(54..56, self.cache_op);
e.set_src_cbuf(23..42, &cb);
e.set_src_cbuf(23..42, cb);
}
SrcRef::Zero | SrcRef::Reg(_) => {
e.set_opcode(0x798, 2);
@ -2440,7 +2440,7 @@ impl SM32Op for OpSuStGa {
};
e.set_su_ga_offset_mode(8..10, self.offset_mode);
e.set_src_cbuf(23..42, &cb);
e.set_src_cbuf(23..42, cb);
e.set_st_cache_op(54..56, self.cache_op);
}
SrcRef::Zero | SrcRef::Reg(_) => {