diff --git a/src/compiler/rust/proc/as_slice.rs b/src/compiler/rust/proc/as_slice.rs
index 20a338923a6..b9aa8096762 100644
--- a/src/compiler/rust/proc/as_slice.rs
+++ b/src/compiler/rust/proc/as_slice.rs
@@ -87,7 +87,7 @@ pub fn derive_as_slice(
             if let Fields::Named(named) = s.fields {
                 for f in named.named {
                     let f_count = count_type(&f.ty, slice_type);
-                    let f_attr = get_attr(&f, &attr_name);
+                    let f_attr = get_attr(&f, attr_name);
 
                     if f_count > 0 {
                         assert!(
diff --git a/src/nouveau/compiler/nak/assign_regs.rs b/src/nouveau/compiler/nak/assign_regs.rs
index 4142038dc28..82de4014b12 100644
--- a/src/nouveau/compiler/nak/assign_regs.rs
+++ b/src/nouveau/compiler/nak/assign_regs.rs
@@ -685,7 +685,7 @@ impl<'a> VecRegAllocator<'a> {
 
         if let Some(reg) = self.ra.try_find_unused_reg_range(0, comps, align, 0)
         {
-            return self.assign_pin_vec_reg(&vec, reg);
+            return self.assign_pin_vec_reg(vec, reg);
         }
 
         let reg = self
@@ -695,7 +695,7 @@ impl<'a> VecRegAllocator<'a> {
         for c in 0..comps {
             self.evict_reg_if_used(reg + u32::from(c));
         }
-        self.assign_pin_vec_reg(&vec, reg)
+        self.assign_pin_vec_reg(vec, reg)
     }
 
     pub fn free_killed(&mut self, killed: &KillSet) {
diff --git a/src/nouveau/compiler/nak/calc_instr_deps.rs b/src/nouveau/compiler/nak/calc_instr_deps.rs
index 84ad1112dbf..2c10fa872a4 100644
--- a/src/nouveau/compiler/nak/calc_instr_deps.rs
+++ b/src/nouveau/compiler/nak/calc_instr_deps.rs
@@ -542,7 +542,7 @@ impl TexQueueSimulationState {
 
         // Push registers (if we are a tex instruction)
         // We might need to insert a barrier if the queue is full
-        let push_level = if instr_needs_texbar(&instr) {
+        let push_level = if instr_needs_texbar(instr) {
             let dst = instr.dsts()[0].as_reg().unwrap();
             self.push(*dst)
         } else {
@@ -615,7 +615,7 @@ fn insert_texture_barriers(f: &mut Function, sm: &ShaderModelInfo) {
 
             for instr in block.instrs.iter() {
                 // Ignore the barrier, we will recompute this later
-                let _bar = sim.visit_instr(&instr);
+                let _bar = sim.visit_instr(instr);
             }
 
             if *sim_out == sim {
diff --git a/src/nouveau/compiler/nak/sm20.rs b/src/nouveau/compiler/nak/sm20.rs
index 2d98273542d..bec95783f59 100644
--- a/src/nouveau/compiler/nak/sm20.rs
+++ b/src/nouveau/compiler/nak/sm20.rs
@@ -484,7 +484,7 @@ impl SM20Encoder<'_> {
         self.set_opcode(unit, opcode);
         self.set_dst(14..20, dst);
 
-        match AluSrc::from_src(Some(&src)) {
+        match AluSrc::from_src(Some(src)) {
             AluSrc::None => panic!("src is always Some"),
             AluSrc::Reg(reg) => {
                 self.set_reg(26..32, reg);
diff --git a/src/nouveau/compiler/nak/sm30_instr_latencies.rs b/src/nouveau/compiler/nak/sm30_instr_latencies.rs
index 5fe9346784b..53561ad543d 100644
--- a/src/nouveau/compiler/nak/sm30_instr_latencies.rs
+++ b/src/nouveau/compiler/nak/sm30_instr_latencies.rs
@@ -155,7 +155,7 @@ where
         debug_assert!(bv.bits() == 8 * 7);
 
         for (i, instr) in sched_chunk.iter().enumerate() {
-            encoder.encode_instr(&instr, &labels, &mut encoded);
+            encoder.encode_instr(instr, &labels, &mut encoded);
 
             let sched = calc_instr_sched(prev_op, &instr.op, &instr.deps);
             bv.set_field(i * 8..(i + 1) * 8, sched);
diff --git a/src/nouveau/compiler/nak/sm32.rs b/src/nouveau/compiler/nak/sm32.rs
index 3ad5b4be013..df903944c86 100644
--- a/src/nouveau/compiler/nak/sm32.rs
+++ b/src/nouveau/compiler/nak/sm32.rs
@@ -642,7 +642,7 @@ impl SM32Op for OpRro {
             }
             SrcRef::CBuf(cb) => {
                 e.set_opcode(0x648, 2);
-                e.set_src_cbuf(23..42, &cb);
+                e.set_src_cbuf(23..42, cb);
             }
             _ => panic!("Invalid Rro src"),
         }
@@ -1087,7 +1087,7 @@ impl SM32Op for OpFlo {
             }
             SrcRef::CBuf(cb) => {
                 e.set_opcode(0x618, 2);
-                e.set_src_cbuf(23..42, &cb);
+                e.set_src_cbuf(23..42, cb);
             }
             _ => panic!("Invalid flo src"),
         }
@@ -2387,7 +2387,7 @@ impl SM32Op for OpSuLdGa {
                 e.set_mem_type(56..59, self.mem_type);
 
                 e.set_ld_cache_op(54..56, self.cache_op);
-                e.set_src_cbuf(23..42, &cb);
+                e.set_src_cbuf(23..42, cb);
             }
             SrcRef::Zero | SrcRef::Reg(_) => {
                 e.set_opcode(0x798, 2);
@@ -2440,7 +2440,7 @@ impl SM32Op for OpSuStGa {
                 };
 
                 e.set_su_ga_offset_mode(8..10, self.offset_mode);
-                e.set_src_cbuf(23..42, &cb);
+                e.set_src_cbuf(23..42, cb);
                 e.set_st_cache_op(54..56, self.cache_op);
             }
             SrcRef::Zero | SrcRef::Reg(_) => {