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radv/sdma: simplify configuring the number of uncompressed DCC blocks
SDMA doesn't support MSAA, so the value can be V_028C78_MAX_BLOCK_SIZE_256B. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34517>
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3 changed files with 2 additions and 5 deletions
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@ -1464,7 +1464,7 @@ radv_surface_max_layer_count(struct radv_image_view *iview)
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: (iview->vk.base_array_layer + iview->vk.layer_count);
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}
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unsigned
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static unsigned
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radv_get_dcc_max_uncompressed_block_size(const struct radv_device *device, const struct radv_image *image)
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{
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const struct radv_physical_device *pdev = radv_device_physical(device);
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@ -358,8 +358,6 @@ unsigned radv_get_default_max_sample_dist(int log_samples);
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void radv_emit_default_sample_locations(const struct radv_physical_device *pdev, struct radeon_cmdbuf *cs,
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int nr_samples);
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unsigned radv_get_dcc_max_uncompressed_block_size(const struct radv_device *device, const struct radv_image *image);
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struct radv_color_buffer_info {
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struct ac_cb_surface ac;
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};
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@ -208,11 +208,10 @@ radv_sdma_get_metadata_config(const struct radv_device *const device, const stru
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const uint32_t number_type = radv_translate_buffer_numformat(desc, vk_format_get_first_non_void_channel(format));
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const uint32_t surface_type = radv_sdma_surface_type_from_aspect_mask(subresource.aspectMask);
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const uint32_t max_comp_block_size = surf->u.gfx9.color.dcc.max_compressed_block_size;
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const uint32_t max_uncomp_block_size = radv_get_dcc_max_uncompressed_block_size(device, image);
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const uint32_t pipe_aligned = radv_htile_enabled(image, subresource.mipLevel) || surf->u.gfx9.color.dcc.pipe_aligned;
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return data_format | alpha_is_on_msb << 8 | number_type << 9 | surface_type << 12 | max_comp_block_size << 24 |
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max_uncomp_block_size << 26 | pipe_aligned << 31;
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V_028C78_MAX_BLOCK_SIZE_256B << 26 | pipe_aligned << 31;
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}
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static uint32_t
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