fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-01-07 06:30:11 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

i915g: implement unfenced relocs for textures using tiling bits

Browse source 
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Jakob Bornecrantz <wallbraker@gmail.com>
Signed-off-by: Jakob Bornecrantz <wallbraker@gmail.com>
This commit is contained in:
Daniel Vetter 2010-12-01 21:03:13 +01:00 • committed by Jakob Bornecrantz
parent a95e694eaf
commit f34fd58ec9
3 changed files with 20 additions and 5 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/gallium/drivers/i915/i915_reg.h
View file

@ -753,7 +753,7 @@
#define MT_COMPRESS_DXT1_RGB (4<<3)
#define MS3_USE_FENCE_REGS (1<<2)
#define MS3_TILED_SURFACE (1<<1)
#define MS3_TILE_WALK (1<<0)
#define MS3_TILE_WALK_Y (1<<0)
#define MS4_PITCH_SHIFT 21
#define MS4_CUBE_FACE_ENA_NEGX (1<<20)

3
src/gallium/drivers/i915/i915_state_emit.c
View file

@ -308,12 +308,11 @@ i915_emit_hardware_state(struct i915_context *i915 )
if (enabled & (1 << unit)) {
struct i915_texture *texture = i915_texture(i915->fragment_sampler_views[unit]->texture);
struct i915_winsys_buffer *buf = texture->buffer;
uint offset = 0;
assert(buf);
count++;
OUT_RELOC_FENCED(buf, I915_USAGE_SAMPLER, offset);
OUT_RELOC(buf, I915_USAGE_SAMPLER, 0);
OUT_BATCH(i915->current.texbuffer[unit][0]); /* MS3 */
OUT_BATCH(i915->current.texbuffer[unit][1]); /* MS4 */
}

20
src/gallium/drivers/i915/i915_state_sampler.c
View file

@ -243,6 +243,23 @@ static uint translate_texture_format(enum pipe_format pipeFormat)
}
}
static inline uint32_t
ms3_tiling_bits(enum i915_winsys_buffer_tile tiling)
{
uint32_t tiling_bits = 0;
switch (tiling) {
case I915_TILE_Y:
tiling_bits |= MS3_TILE_WALK_Y;
case I915_TILE_X:
tiling_bits |= MS3_TILED_SURFACE;
case I915_TILE_NONE:
break;
}
return tiling_bits;
}
static void update_map(struct i915_context *i915,
uint unit,
const struct i915_texture *tex,
@ -254,7 +271,6 @@ static void update_map(struct i915_context *i915,
const uint width = pt->width0, height = pt->height0, depth = pt->depth0;
const uint num_levels = pt->last_level;
unsigned max_lod = num_levels * 4;
unsigned tiled = MS3_USE_FENCE_REGS;
assert(tex);
assert(width);
@ -272,7 +288,7 @@ static void update_map(struct i915_context *i915,
(((height - 1) << MS3_HEIGHT_SHIFT)
| ((width - 1) << MS3_WIDTH_SHIFT)
| format
| tiled);
| ms3_tiling_bits(tex->tiling));
/*
* XXX When min_filter != mag_filter and there's just one mipmap level,