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i915g: implement unfenced color&depth buffer using tiling bits
v2: Clarify tiling bit calculation as suggested by Chris Wilson. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Jakob Bornecrantz <wallbraker@gmail.com> Signed-off-by: Jakob Bornecrantz <wallbraker@gmail.com>
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2ff0879a63
commit
a95e694eaf
2 changed files with 22 additions and 8 deletions
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@ -193,8 +193,7 @@ struct i915_velems_state {
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};
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struct i915_context
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{
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struct i915_context {
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struct pipe_context base;
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struct i915_winsys *iws;
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@ -86,6 +86,22 @@ framebuffer_size(const struct pipe_framebuffer_state *fb,
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}
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}
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static inline uint32_t
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buf_3d_tiling_bits(enum i915_winsys_buffer_tile tiling)
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{
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uint32_t tiling_bits = 0;
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switch (tiling) {
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case I915_TILE_Y:
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tiling_bits |= BUF_3D_TILE_WALK_Y;
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case I915_TILE_X:
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tiling_bits |= BUF_3D_TILED_SURFACE;
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case I915_TILE_NONE:
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break;
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}
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return tiling_bits;
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}
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/* Push the state into the sarea and/or texture memory.
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*/
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@ -220,17 +236,17 @@ i915_emit_hardware_state(struct i915_context *i915 )
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struct pipe_surface *depth_surface = i915->framebuffer.zsbuf;
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if (cbuf_surface) {
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unsigned ctile = BUF_3D_USE_FENCE;
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struct i915_texture *tex = i915_texture(cbuf_surface->texture);
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uint32_t tiling_bits = 0;
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assert(tex);
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OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
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OUT_BATCH(BUF_3D_ID_COLOR_BACK |
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BUF_3D_PITCH(tex->stride) | /* pitch in bytes */
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ctile);
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buf_3d_tiling_bits(tex->tiling));
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OUT_RELOC_FENCED(tex->buffer,
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OUT_RELOC(tex->buffer,
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I915_USAGE_RENDER,
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cbuf_surface->offset);
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}
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@ -238,7 +254,6 @@ i915_emit_hardware_state(struct i915_context *i915 )
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/* What happens if no zbuf??
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*/
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if (depth_surface) {
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unsigned ztile = BUF_3D_USE_FENCE;
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struct i915_texture *tex = i915_texture(depth_surface->texture);
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assert(tex);
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@ -247,9 +262,9 @@ i915_emit_hardware_state(struct i915_context *i915 )
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assert(tex);
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OUT_BATCH(BUF_3D_ID_DEPTH |
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BUF_3D_PITCH(tex->stride) | /* pitch in bytes */
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ztile);
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buf_3d_tiling_bits(tex->tiling));
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OUT_RELOC_FENCED(tex->buffer,
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OUT_RELOC(tex->buffer,
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I915_USAGE_RENDER,
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depth_surface->offset);
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}
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