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nir-to-tgsi: Fix handling of partial writemasks on SSA/REG decls.

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In nouveau's PBO path with GS support and no VS layer export, we got:

        intrinsic store_output (ssa_1, ssa_0) (0, 15, 0, 160, 128) /* base=0 */ /* wrmask=xyzw */ /* component=0 */ /* src_type=float32 */ /* location=0 slots=1 */     /* out_pos */
        [...]
        vec3 32 ssa_4 = mov ssa_3.xxx
        intrinsic store_output (ssa_4, ssa_0) (0, 4, 0, 160, 128) /* base=0 */ /* wrmask=z */ /* component=0 */ /* src_type=float32 */ /* location=0 slots=1 *//* out_pos */

The mov's SSA value we would decide we could store directly to the output,
since nothing else used it.  However, the store has a writemask, and the
ALU op was stomping over it instead of ANDing with the output decl's
existing writemask.

Fixes: f79f382c81 ("nir_to_tgsi: Store directly to TGSI outputs when possible.")
Closes: #4380
Tested-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9376>
This commit is contained in:
Eric Anholt 2021-03-02 12:10:49 -08:00 • committed by Marge Bot
parent e20e85f01e
commit f301eec9a3
1 changed files with 2 additions and 2 deletions
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4
src/gallium/auxiliary/nir/nir_to_tgsi.c
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@ -699,9 +699,9 @@ ntt_emit_alu(struct ntt_compile *c, nir_alu_instr *instr)
dst.Saturate = true;
if (dst_64)
dst.WriteMask = ntt_64bit_write_mask(instr->dest.write_mask);
dst = ureg_writemask(dst, ntt_64bit_write_mask(instr->dest.write_mask));
else
dst.WriteMask = instr->dest.write_mask;
dst = ureg_writemask(dst, instr->dest.write_mask);
static enum tgsi_opcode op_map[][2] = {
[nir_op_mov] = { TGSI_OPCODE_MOV, TGSI_OPCODE_MOV },