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nir_to_tgsi: Store directly to TGSI outputs when possible.
Saves emitting a MOV at the end of the program to store the output. softpipe glmark2 -b buffer +9.73451% +/- 3.17924% (n=6) softpipe glmark2 -b build +5.57621% +/- 1.35074% (n=9) Reviewed-by: Matt Turner <mattst88@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8023>
This commit is contained in:
Eric Anholt
Marge Bot
parent
f6e35e5fd0
commit
f79f382c81
1 changed files with 144 additions and 83 deletions
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@ -162,6 +162,124 @@ ntt_tgsi_var_usage_mask(const struct nir_variable *var)
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glsl_type_is_64bit(type_without_array));
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}
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static struct ureg_dst
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ntt_store_output_decl(struct ntt_compile *c, nir_intrinsic_instr *instr, uint32_t *frac)
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{
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nir_io_semantics semantics = nir_intrinsic_io_semantics(instr);
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int base = nir_intrinsic_base(instr);
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*frac = nir_intrinsic_component(instr);
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bool is_64 = nir_src_bit_size(instr->src[0]) == 64;
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struct ureg_dst out;
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if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
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if (semantics.location == FRAG_RESULT_COLOR)
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ureg_property(c->ureg, TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS, 1);
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unsigned semantic_name, semantic_index;
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tgsi_get_gl_frag_result_semantic(semantics.location,
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&semantic_name, &semantic_index);
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semantic_index += semantics.dual_source_blend_index;
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switch (semantics.location) {
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case FRAG_RESULT_DEPTH:
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*frac = 2; /* z write is the to the .z channel in TGSI */
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break;
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case FRAG_RESULT_STENCIL:
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*frac = 1;
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break;
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default:
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break;
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}
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out = ureg_DECL_output(c->ureg, semantic_name, semantic_index);
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} else {
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unsigned semantic_name, semantic_index;
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ntt_get_gl_varying_semantic(c, semantics.location,
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&semantic_name, &semantic_index);
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uint32_t usage_mask = ntt_tgsi_usage_mask(*frac,
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instr->num_components,
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is_64);
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uint32_t gs_streams = semantics.gs_streams;
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for (int i = 0; i < 4; i++) {
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if (!(usage_mask & (1 << i)))
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gs_streams &= ~(0x3 << 2 * i);
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}
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/* No driver appears to use array_id of outputs. */
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unsigned array_id = 0;
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/* This bit is lost in the i/o semantics, but it's unused in in-tree
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* drivers.
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*/
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bool invariant = false;
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out = ureg_DECL_output_layout(c->ureg,
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semantic_name, semantic_index,
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gs_streams,
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base,
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usage_mask,
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array_id,
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semantics.num_slots,
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invariant);
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}
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unsigned write_mask = nir_intrinsic_write_mask(instr);
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if (is_64) {
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write_mask = ntt_64bit_write_mask(write_mask);
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if (*frac >= 2)
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write_mask = write_mask << 2;
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} else {
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write_mask = write_mask << *frac;
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}
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return ureg_writemask(out, write_mask);
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}
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/* If this reg or SSA def is used only for storing an output, then in the simple
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* cases we can write directly to the TGSI output instead of having store_output
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* emit its own MOV.
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*/
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static bool
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ntt_try_store_in_tgsi_output(struct ntt_compile *c, struct ureg_dst *dst,
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struct list_head *uses, struct list_head *if_uses)
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{
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*dst = ureg_dst_undef();
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switch (c->s->info.stage) {
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case MESA_SHADER_FRAGMENT:
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case MESA_SHADER_VERTEX:
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break;
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default:
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/* tgsi_exec (at least) requires that output stores happen per vertex
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* emitted, you don't get to reuse a previous output value for the next
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* vertex.
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*/
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return false;
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}
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if (!list_is_empty(if_uses) || !list_is_singular(uses))
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return false;
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nir_src *src = list_first_entry(uses, nir_src, use_link);
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if (src->parent_instr->type != nir_instr_type_intrinsic)
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return false;
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nir_intrinsic_instr *intr = nir_instr_as_intrinsic(src->parent_instr);
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if (intr->intrinsic != nir_intrinsic_store_output ||
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!nir_src_is_const(intr->src[1])) {
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return false;
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}
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uint32_t frac;
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*dst = ntt_store_output_decl(c, intr, &frac);
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dst->Index += nir_src_as_uint(intr->src[1]);
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return frac == 0;
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}
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static void
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ntt_setup_inputs(struct ntt_compile *c)
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{
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@ -297,16 +415,18 @@ ntt_setup_registers(struct ntt_compile *c, struct exec_list *list)
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struct ureg_dst decl;
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if (nir_reg->num_array_elems == 0) {
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uint32_t write_mask = BITFIELD_MASK(nir_reg->num_components);
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if (nir_reg->bit_size == 64) {
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if (nir_reg->num_components > 2) {
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fprintf(stderr, "NIR-to-TGSI: error: %d-component NIR r%d\n",
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nir_reg->num_components, nir_reg->index);
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if (!ntt_try_store_in_tgsi_output(c, &decl, &nir_reg->uses, &nir_reg->if_uses)) {
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if (nir_reg->bit_size == 64) {
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if (nir_reg->num_components > 2) {
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fprintf(stderr, "NIR-to-TGSI: error: %d-component NIR r%d\n",
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nir_reg->num_components, nir_reg->index);
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}
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write_mask = ntt_64bit_write_mask(write_mask);
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}
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write_mask = ntt_64bit_write_mask(write_mask);
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decl = ureg_writemask(ureg_DECL_temporary(c->ureg), write_mask);
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}
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decl = ureg_writemask(ureg_DECL_temporary(c->ureg), write_mask);
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} else {
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decl = ureg_DECL_array_temporary(c->ureg, nir_reg->num_array_elems,
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true);
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@ -455,13 +575,15 @@ ntt_swizzle_for_write_mask(struct ureg_src src, uint32_t write_mask)
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static struct ureg_dst *
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ntt_get_ssa_def_decl(struct ntt_compile *c, nir_ssa_def *ssa)
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{
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struct ureg_dst temp = ureg_DECL_temporary(c->ureg);
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uint32_t writemask = BITSET_MASK(ssa->num_components);
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if (ssa->bit_size == 64)
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writemask = ntt_64bit_write_mask(writemask);
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c->ssa_temp[ssa->index] = ureg_writemask(temp, writemask);
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struct ureg_dst dst;
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if (!ntt_try_store_in_tgsi_output(c, &dst, &ssa->uses, &ssa->if_uses))
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dst = ureg_DECL_temporary(c->ureg);
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c->ssa_temp[ssa->index] = ureg_writemask(dst, writemask);
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return &c->ssa_temp[ssa->index];
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}
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@ -997,7 +1119,9 @@ ntt_ureg_src_dimension_indirect(struct ntt_compile *c, struct ureg_src usrc,
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{
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if (nir_src_is_const(src)) {
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return ureg_src_dimension(usrc, nir_src_as_uint(src));
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} else {
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}
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else
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{
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return ureg_src_dimension_indirect(usrc,
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ntt_reladdr(c, ntt_get_src(c, src)),
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0);
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@ -1445,71 +1569,19 @@ ntt_emit_load_input(struct ntt_compile *c, nir_intrinsic_instr *instr)
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static void
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ntt_emit_store_output(struct ntt_compile *c, nir_intrinsic_instr *instr)
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{
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/* TODO: When making an SSA def's storage, we should check if it's only
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* used as the source of a store_output and point it at our
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* TGSI_FILE_OUTPUT instead of generating the extra MOV here.
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*/
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uint32_t base = nir_intrinsic_base(instr);
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struct ureg_src src = ntt_get_src(c, instr->src[0]);
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bool is_64 = nir_src_bit_size(instr->src[0]) == 64;
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struct ureg_dst out;
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nir_io_semantics semantics = nir_intrinsic_io_semantics(instr);
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uint32_t frac = nir_intrinsic_component(instr);
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if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
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if (semantics.location == FRAG_RESULT_COLOR)
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ureg_property(c->ureg, TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS, 1);
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unsigned semantic_name, semantic_index;
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tgsi_get_gl_frag_result_semantic(semantics.location,
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&semantic_name, &semantic_index);
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semantic_index += semantics.dual_source_blend_index;
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out = ureg_DECL_output(c->ureg, semantic_name, semantic_index);
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switch (semantics.location) {
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case FRAG_RESULT_DEPTH:
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frac = 2; /* z write is the to the .z channel in TGSI */
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break;
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case FRAG_RESULT_STENCIL:
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frac = 1;
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break;
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default:
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break;
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}
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} else {
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unsigned semantic_name, semantic_index;
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ntt_get_gl_varying_semantic(c, semantics.location,
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&semantic_name, &semantic_index);
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uint32_t usage_mask = ntt_tgsi_usage_mask(frac,
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instr->num_components,
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is_64);
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uint32_t gs_streams = semantics.gs_streams;
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for (int i = 0; i < 4; i++) {
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if (!(usage_mask & (1 << i)))
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gs_streams &= ~(0x3 << 2 * i);
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}
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/* No driver appears to use array_id of outputs. */
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unsigned array_id = 0;
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/* This bit is lost in the i/o semantics, but it's unused in in-tree
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* drivers.
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if (src.File == TGSI_FILE_OUTPUT) {
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/* If our src is the output file, that's an indication that we were able
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* to emit the output stores in the generating instructions and we have
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* nothing to do here.
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*/
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bool invariant = false;
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out = ureg_DECL_output_layout(c->ureg,
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semantic_name, semantic_index,
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gs_streams,
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base,
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usage_mask,
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array_id,
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semantics.num_slots,
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invariant);
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return;
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}
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uint32_t frac;
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struct ureg_dst out = ntt_store_output_decl(c, instr, &frac);
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if (instr->intrinsic == nir_intrinsic_store_per_vertex_output) {
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out = ntt_ureg_dst_indirect(c, out, instr->src[2]);
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out = ntt_ureg_dst_dimension_indirect(c, out, instr->src[1]);
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@ -1517,24 +1589,13 @@ ntt_emit_store_output(struct ntt_compile *c, nir_intrinsic_instr *instr)
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out = ntt_ureg_dst_indirect(c, out, instr->src[1]);
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}
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unsigned write_mask = nir_intrinsic_write_mask(instr);
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if (is_64) {
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write_mask = ntt_64bit_write_mask(write_mask);
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if (frac >= 2)
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write_mask = write_mask << 2;
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} else {
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write_mask = write_mask << frac;
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}
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uint8_t swizzle[4] = { 0, 0, 0, 0 };
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for (int i = frac; i <= 4; i++) {
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if (write_mask & (1 << i))
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if (out.WriteMask & (1 << i))
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swizzle[i] = i - frac;
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}
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src = ureg_swizzle(src, swizzle[0], swizzle[1], swizzle[2], swizzle[3]);
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out = ureg_writemask(out, write_mask);
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ureg_MOV(c->ureg, out, src);
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ntt_reladdr_dst_put(c, out);
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