From f28552b804ac6f0b1e452c2241da95b32dde3b04 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Wed, 18 Aug 2021 15:21:28 -0400 Subject: [PATCH] radeonsi: don't use SQ_NON_EVENT before GE_PC_ALLOC for better perf on Navi1x SQ_NON_EVENT was originally meant to fix a perf issue on Navi1x, but using the event actually makes the perf worse. This improves perf for viewperf/snx. Acked-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/gallium/drivers/radeonsi/si_cp_reg_shadowing.c | 6 ------ src/gallium/drivers/radeonsi/si_state_shaders.c | 7 ------- 2 files changed, 13 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_cp_reg_shadowing.c b/src/gallium/drivers/radeonsi/si_cp_reg_shadowing.c index f21f43373d7..572905b84f8 100644 --- a/src/gallium/drivers/radeonsi/si_cp_reg_shadowing.c +++ b/src/gallium/drivers/radeonsi/si_cp_reg_shadowing.c @@ -70,12 +70,6 @@ si_create_shadowing_ib_preamble(struct si_context *sctx) { struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); - if (sctx->chip_class == GFX10) { - /* SQ_NON_EVENT must be emitted before GE_PC_ALLOC is written. */ - si_pm4_cmd_add(pm4, PKT3(PKT3_EVENT_WRITE, 0, 0)); - si_pm4_cmd_add(pm4, EVENT_TYPE(V_028A90_SQ_NON_EVENT) | EVENT_INDEX(0)); - } - if (sctx->screen->dpbb_allowed) { si_pm4_cmd_add(pm4, PKT3(PKT3_EVENT_WRITE, 0, 0)); si_pm4_cmd_add(pm4, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0)); diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c index d6b92e175a0..cd8387ff9da 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.c +++ b/src/gallium/drivers/radeonsi/si_state_shaders.c @@ -983,13 +983,6 @@ static void gfx10_emit_ge_pc_alloc(struct si_context *sctx, unsigned value) struct radeon_cmdbuf *cs = &sctx->gfx_cs; radeon_begin(cs); - - if (sctx->chip_class == GFX10) { - /* SQ_NON_EVENT must be emitted before GE_PC_ALLOC is written. */ - radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); - radeon_emit(cs, EVENT_TYPE(V_028A90_SQ_NON_EVENT) | EVENT_INDEX(0)); - } - radeon_set_uconfig_reg(cs, R_030980_GE_PC_ALLOC, value); radeon_end();