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https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-04-05 08:10:35 +02:00
radv/meta: convert the copy VRS to HTILE pipelines to vk_meta
This pipeline was already always on-demand. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32744>
This commit is contained in:
parent
88ffeb61ae
commit
f27bee04ce
4 changed files with 40 additions and 54 deletions
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@ -562,7 +562,6 @@ radv_device_finish_meta(struct radv_device *device)
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radv_device_finish_meta_resolve_fragment_state(device);
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radv_device_finish_meta_fmask_expand_state(device);
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radv_device_finish_meta_dcc_retile_state(device);
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radv_device_finish_meta_copy_vrs_htile_state(device);
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radv_device_finish_meta_fmask_copy_state(device);
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radv_store_meta_pipeline(device);
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@ -140,8 +140,6 @@ void radv_device_finish_meta_fmask_expand_state(struct radv_device *device);
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void radv_device_finish_meta_dcc_retile_state(struct radv_device *device);
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void radv_device_finish_meta_copy_vrs_htile_state(struct radv_device *device);
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VkResult radv_device_init_null_accel_struct(struct radv_device *device);
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VkResult radv_device_init_accel_struct_build_state(struct radv_device *device);
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void radv_device_finish_accel_struct_build_state(struct radv_device *device);
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@ -11,17 +11,6 @@
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#include "vk_common_entrypoints.h"
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#include "vk_format.h"
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void
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radv_device_finish_meta_copy_vrs_htile_state(struct radv_device *device)
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{
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struct radv_meta_state *state = &device->meta_state;
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radv_DestroyPipeline(radv_device_to_handle(device), state->copy_vrs_htile_pipeline, &state->alloc);
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radv_DestroyPipelineLayout(radv_device_to_handle(device), state->copy_vrs_htile_p_layout, &state->alloc);
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device->vk.dispatch_table.DestroyDescriptorSetLayout(radv_device_to_handle(device), state->copy_vrs_htile_ds_layout,
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&state->alloc);
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}
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static nir_shader *
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build_copy_vrs_htile_shader(struct radv_device *device, struct radeon_surf *surf)
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{
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@ -104,9 +93,10 @@ build_copy_vrs_htile_shader(struct radv_device *device, struct radeon_surf *surf
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}
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static VkResult
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create_pipeline(struct radv_device *device, struct radeon_surf *surf)
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get_pipeline(struct radv_device *device, struct radv_image *image, VkPipeline *pipeline_out,
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VkPipelineLayout *layout_out)
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{
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struct radv_meta_state *state = &device->meta_state;
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const char *key_data = "radv-copy-vrs-htile";
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VkResult result;
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const VkDescriptorSetLayoutBinding bindings[] = {
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@ -124,46 +114,50 @@ create_pipeline(struct radv_device *device, struct radeon_surf *surf)
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},
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};
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result = radv_meta_create_descriptor_set_layout(device, 2, bindings, &state->copy_vrs_htile_ds_layout);
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if (result != VK_SUCCESS)
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return result;
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const VkDescriptorSetLayoutCreateInfo desc_info = {
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.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
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.flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT,
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.bindingCount = 2,
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.pBindings = bindings,
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};
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const VkPushConstantRange pc_range = {
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.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
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.size = 20,
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};
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result = radv_meta_create_pipeline_layout(device, &state->copy_vrs_htile_ds_layout, 1, &pc_range,
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&state->copy_vrs_htile_p_layout);
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result = vk_meta_get_pipeline_layout(&device->vk, &device->meta_state.device, &desc_info, &pc_range, key_data,
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strlen(key_data), layout_out);
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if (result != VK_SUCCESS)
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return result;
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nir_shader *cs = build_copy_vrs_htile_shader(device, surf);
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result =
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radv_meta_create_compute_pipeline(device, cs, state->copy_vrs_htile_p_layout, &state->copy_vrs_htile_pipeline);
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ralloc_free(cs);
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return result;
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}
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static VkResult
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get_pipeline(struct radv_device *device, struct radv_image *image, VkPipeline *pipeline_out)
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{
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struct radv_meta_state *state = &device->meta_state;
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VkResult result = VK_SUCCESS;
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mtx_lock(&state->mtx);
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if (!state->copy_vrs_htile_pipeline) {
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result = create_pipeline(device, &image->planes[0].surface);
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if (result != VK_SUCCESS)
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goto fail;
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VkPipeline pipeline_from_cache = vk_meta_lookup_pipeline(&device->meta_state.device, key_data, strlen(key_data));
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if (pipeline_from_cache != VK_NULL_HANDLE) {
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*pipeline_out = pipeline_from_cache;
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return VK_SUCCESS;
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}
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*pipeline_out = state->copy_vrs_htile_pipeline;
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nir_shader *cs = build_copy_vrs_htile_shader(device, &image->planes[0].surface);
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fail:
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mtx_unlock(&state->mtx);
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const VkPipelineShaderStageCreateInfo stage_info = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
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.stage = VK_SHADER_STAGE_COMPUTE_BIT,
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.module = vk_shader_module_handle_from_nir(cs),
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.pName = "main",
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.pSpecializationInfo = NULL,
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};
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const VkComputePipelineCreateInfo pipeline_info = {
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.sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
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.stage = stage_info,
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.flags = 0,
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.layout = *layout_out,
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};
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result = vk_meta_create_compute_pipeline(&device->vk, &device->meta_state.device, &pipeline_info, key_data,
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strlen(key_data), pipeline_out);
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ralloc_free(cs);
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return result;
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}
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@ -172,14 +166,14 @@ radv_copy_vrs_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image_view *
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struct radv_image *dst_image, struct radv_buffer *htile_buffer, bool read_htile_value)
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{
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struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
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struct radv_meta_state *state = &device->meta_state;
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struct radv_meta_saved_state saved_state;
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VkPipelineLayout layout;
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VkPipeline pipeline;
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VkResult result;
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assert(radv_image_has_htile(dst_image));
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result = get_pipeline(device, dst_image, &pipeline);
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result = get_pipeline(device, dst_image, &pipeline, &layout);
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if (result != VK_SUCCESS) {
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vk_command_buffer_set_error(&cmd_buffer->vk, result);
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return;
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@ -196,7 +190,7 @@ radv_copy_vrs_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image_view *
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radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE, pipeline);
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radv_meta_push_descriptor_set(
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cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE, state->copy_vrs_htile_p_layout, 0, 2,
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cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE, layout, 0, 2,
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(VkWriteDescriptorSet[]){{.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
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.dstBinding = 0,
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.dstArrayElement = 0,
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@ -227,8 +221,8 @@ radv_copy_vrs_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image_view *
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read_htile_value,
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};
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vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), state->copy_vrs_htile_p_layout,
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VK_SHADER_STAGE_COMPUTE_BIT, 0, 20, constants);
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vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), layout, VK_SHADER_STAGE_COMPUTE_BIT, 0, 20,
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constants);
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uint32_t width = DIV_ROUND_UP(rect->extent.width, 8);
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uint32_t height = DIV_ROUND_UP(rect->extent.height, 8);
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@ -115,11 +115,6 @@ struct radv_meta_state {
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VkPipelineLayout clear_htile_mask_p_layout;
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VkDescriptorSetLayout clear_htile_mask_ds_layout;
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/* Copy VRS into HTILE. */
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VkPipeline copy_vrs_htile_pipeline;
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VkPipelineLayout copy_vrs_htile_p_layout;
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VkDescriptorSetLayout copy_vrs_htile_ds_layout;
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/* Clear DCC with comp-to-single. */
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VkPipeline clear_dcc_comp_to_single_pipeline[2]; /* 0: 1x, 1: 2x/4x/8x */
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VkPipelineLayout clear_dcc_comp_to_single_p_layout;
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