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gallium/ntt: lower uniforms to ubo

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NTT doesn't handle uniforms, and requires them to have been lowered to
UBOs. But for drivers that don't set
nir_shader_compiler_options::lower_uniforms_to_ubo to true, this won't
have happened yet. Neither Zink nor V3D sets this option, and in the
case of Zink this isn't trivial to change.

So let's lower uniforms to UBOs in this case in NTT instead.

Fixes: 03c60762f5 ("gallium/ntt: Fix load_ubo_vec4 buffer index setup.")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4047
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8365>
This commit is contained in:
Erik Faye-Lund 2021-01-07 16:54:18 +01:00 • committed by Marge Bot
parent 28a141e325
commit f1b51d472a
1 changed files with 6 additions and 0 deletions
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6
src/gallium/auxiliary/nir/nir_to_tgsi.c
View file

@ -2554,6 +2554,12 @@ nir_to_tgsi(struct nir_shader *s,
}; };
NIR_PASS_V(s, nir_lower_tex, &lower_tex_options); NIR_PASS_V(s, nir_lower_tex, &lower_tex_options);
if (!original_options->lower_uniforms_to_ubo) {
NIR_PASS_V(s, nir_lower_uniforms_to_ubo,
screen->get_param(screen, PIPE_CAP_PACKED_UNIFORMS) ?
4 : 16);
}
/* Do lowering so we can directly translate f64/i64 NIR ALU ops to TGSI -- /* Do lowering so we can directly translate f64/i64 NIR ALU ops to TGSI --
* TGSI stores up to a vec2 in each slot, so to avoid a whole bunch of op * TGSI stores up to a vec2 in each slot, so to avoid a whole bunch of op
* duplication logic we just make it so that we only see vec2s. * duplication logic we just make it so that we only see vec2s.