From f1b51d472a7b8231b5627fdcaa00740e0ffb64fc Mon Sep 17 00:00:00 2001 From: Erik Faye-Lund Date: Thu, 7 Jan 2021 16:54:18 +0100 Subject: [PATCH] gallium/ntt: lower uniforms to ubo NTT doesn't handle uniforms, and requires them to have been lowered to UBOs. But for drivers that don't set nir_shader_compiler_options::lower_uniforms_to_ubo to true, this won't have happened yet. Neither Zink nor V3D sets this option, and in the case of Zink this isn't trivial to change. So let's lower uniforms to UBOs in this case in NTT instead. Fixes: 03c60762f57 ("gallium/ntt: Fix load_ubo_vec4 buffer index setup.") Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4047 Reviewed-by: Jose Maria Casanova Crespo Reviewed-by: Eric Anholt Part-of: --- src/gallium/auxiliary/nir/nir_to_tgsi.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/gallium/auxiliary/nir/nir_to_tgsi.c b/src/gallium/auxiliary/nir/nir_to_tgsi.c index 01f69df1ac8..da74b2d666b 100644 --- a/src/gallium/auxiliary/nir/nir_to_tgsi.c +++ b/src/gallium/auxiliary/nir/nir_to_tgsi.c @@ -2554,6 +2554,12 @@ nir_to_tgsi(struct nir_shader *s, }; NIR_PASS_V(s, nir_lower_tex, &lower_tex_options); + if (!original_options->lower_uniforms_to_ubo) { + NIR_PASS_V(s, nir_lower_uniforms_to_ubo, + screen->get_param(screen, PIPE_CAP_PACKED_UNIFORMS) ? + 4 : 16); + } + /* Do lowering so we can directly translate f64/i64 NIR ALU ops to TGSI -- * TGSI stores up to a vec2 in each slot, so to avoid a whole bunch of op * duplication logic we just make it so that we only see vec2s.