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pan/model: Redo gpu_prod_id in the model
The current implementation is a bit awkward and becomes tricky when adding support for 64 bit gpu_ids. Rather than keeping a mask of bits in gpu_id to compare with the stored gpu_prod_id value, rely on macro functions for fetching the information required from gpu_id and creating the comparison value. Reviewed-by: Aksel Hjerpbakk <aksel.hjerpbakk@arm.com> Reviewed-by: Eric R. Smith <eric.smith@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40610>
This commit is contained in:
Lars-Ivar Hesselberg Simonsen
Marge Bot
parent
37bdb2b792
commit
f181cc5bca
2 changed files with 54 additions and 41 deletions
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@ -1,5 +1,6 @@
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/*
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* Copyright (C) 2019 Collabora, Ltd.
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* Copyright (C) 2026 Arm Ltd.
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* SPDX-License-Identifier: MIT
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*/
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@ -14,11 +15,9 @@
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#define GPU_REV_R0P3 GPU_REV(0, 3)
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#define GPU_REV_R1P1 GPU_REV(1, 1)
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#define MODEL(gpu_prod_id_, gpu_prod_id_mask_, gpu_variant_, shortname, \
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counters, ...) \
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#define MODEL(gpu_prod_id_, gpu_variant_, shortname, counters, ...) \
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{ \
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.gpu_prod_id = gpu_prod_id_, \
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.gpu_prod_id_mask = gpu_prod_id_mask_, \
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.gpu_variant = gpu_variant_, \
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.name = "Mali-" shortname, \
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.performance_counters = counters, \
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@ -26,19 +25,21 @@
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}
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#define MIDGARD_MODEL(gpu_prod_id, shortname, counters, ...) \
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MODEL(gpu_prod_id << 16, 0xffff0000, 0, shortname, counters, ##__VA_ARGS__)
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MODEL(gpu_prod_id, 0, shortname, counters, ##__VA_ARGS__)
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/* Assume 8 bits per field. This ensures the prod_id is always greater than
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* Midgard's. */
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#define PROD_ID(arch_major, arch_minor, prod_major) \
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(((arch_major) << 16) | ((arch_minor) << 8) | (prod_major))
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#define BIFROST_MODEL(gpu_prod_id, shortname, counters, ...) \
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MODEL(gpu_prod_id << 16, ARCH_MAJOR | ARCH_MINOR | PRODUCT_MAJOR, 0, \
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shortname, counters, ##__VA_ARGS__)
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MODEL(gpu_prod_id, 0, shortname, counters, ##__VA_ARGS__)
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#define VALHALL_MODEL(gpu_prod_id, gpu_variant, shortname, counters, ...) \
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MODEL(gpu_prod_id << 16, ARCH_MAJOR | ARCH_MINOR | PRODUCT_MAJOR, \
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gpu_variant, shortname, counters, ##__VA_ARGS__)
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MODEL(gpu_prod_id, gpu_variant, shortname, counters, ##__VA_ARGS__)
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#define FIFTHGEN_MODEL(gpu_prod_id, gpu_variant, shortname, counters, ...) \
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MODEL(gpu_prod_id << 16, ARCH_MAJOR | ARCH_MINOR | PRODUCT_MAJOR, \
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gpu_variant, shortname, counters, ##__VA_ARGS__)
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MODEL(gpu_prod_id, gpu_variant, shortname, counters, ##__VA_ARGS__)
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#define MODEL_ANISO(rev) .min_rev_anisotropic = GPU_REV_##rev
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@ -73,34 +74,34 @@ const struct pan_model pan_model_list[] = {
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MIDGARD_MODEL(0x860, "T860", "T86x", MODEL_ANISO(NONE), MODEL_TB_SIZES( 8192, 8192)),
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MIDGARD_MODEL(0x880, "T880", "T88x", MODEL_ANISO(NONE), MODEL_TB_SIZES( 8192, 8192)),
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BIFROST_MODEL(0x6000, "G71", "TMIx", MODEL_ANISO(NONE), MODEL_TB_SIZES( 4096, 4096)),
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BIFROST_MODEL(0x6201, "G72", "THEx", MODEL_ANISO(R0P3), MODEL_TB_SIZES( 8192, 4096)),
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BIFROST_MODEL(0x7000, "G51", "TSIx", MODEL_ANISO(R1P1), MODEL_TB_SIZES( 8192, 8192)),
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BIFROST_MODEL(0x7003, "G31", "TDVx", MODEL_ANISO(ALL), MODEL_TB_SIZES( 8192, 8192)),
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BIFROST_MODEL(0x7201, "G76", "TNOx", MODEL_ANISO(ALL), MODEL_TB_SIZES(16384, 8192)),
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BIFROST_MODEL(0x7202, "G52", "TGOx", MODEL_ANISO(ALL), MODEL_TB_SIZES(16384, 8192)),
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BIFROST_MODEL(0x7402, "G52 r1", "TGOx", MODEL_ANISO(ALL), MODEL_TB_SIZES( 8192, 8192)),
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BIFROST_MODEL(PROD_ID(6, 0, 0), "G71", "TMIx", MODEL_ANISO(NONE), MODEL_TB_SIZES( 4096, 4096)),
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BIFROST_MODEL(PROD_ID(6, 2, 1), "G72", "THEx", MODEL_ANISO(R0P3), MODEL_TB_SIZES( 8192, 4096)),
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BIFROST_MODEL(PROD_ID(7, 0, 0), "G51", "TSIx", MODEL_ANISO(R1P1), MODEL_TB_SIZES( 8192, 8192)),
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BIFROST_MODEL(PROD_ID(7, 0, 3), "G31", "TDVx", MODEL_ANISO(ALL), MODEL_TB_SIZES( 8192, 8192)),
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BIFROST_MODEL(PROD_ID(7, 2, 1), "G76", "TNOx", MODEL_ANISO(ALL), MODEL_TB_SIZES(16384, 8192)),
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BIFROST_MODEL(PROD_ID(7, 2, 2), "G52", "TGOx", MODEL_ANISO(ALL), MODEL_TB_SIZES(16384, 8192)),
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BIFROST_MODEL(PROD_ID(7, 4, 2), "G52 r1", "TGOx", MODEL_ANISO(ALL), MODEL_TB_SIZES( 8192, 8192)),
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VALHALL_MODEL(0x9001, 0, "G57", "TNAx", MODEL_ANISO(ALL), MODEL_TB_SIZES(16384, 8192),
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VALHALL_MODEL(PROD_ID(9, 0, 1), 0, "G57", "TNAx", MODEL_ANISO(ALL), MODEL_TB_SIZES(16384, 8192),
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MODEL_RATES(2, 4, 32)),
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VALHALL_MODEL(0x9003, 0, "G57", "TNAx", MODEL_ANISO(ALL), MODEL_TB_SIZES(16384, 8192),
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VALHALL_MODEL(PROD_ID(9, 0, 3), 0, "G57", "TNAx", MODEL_ANISO(ALL), MODEL_TB_SIZES(16384, 8192),
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MODEL_RATES(2, 4, 32)),
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VALHALL_MODEL(0xa807, 0, "G610", "TVIx", MODEL_ANISO(ALL), MODEL_TB_SIZES(32768, 16384),
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VALHALL_MODEL(PROD_ID(10, 8, 7), 0, "G610", "TVIx", MODEL_ANISO(ALL), MODEL_TB_SIZES(32768, 16384),
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MODEL_RATES(4, 8, 64)),
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VALHALL_MODEL(0xac04, 0, "G310v1", "TVAx", MODEL_ANISO(ALL), MODEL_TB_SIZES(16384, 8192),
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VALHALL_MODEL(PROD_ID(10, 12, 4), 0, "G310v1", "TVAx", MODEL_ANISO(ALL), MODEL_TB_SIZES(16384, 8192),
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MODEL_RATES(2, 2, 16)),
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VALHALL_MODEL(0xac04, 1, "G310v2", "TVAx", MODEL_ANISO(ALL), MODEL_TB_SIZES(16384, 8192),
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VALHALL_MODEL(PROD_ID(10, 12, 4), 1, "G310v2", "TVAx", MODEL_ANISO(ALL), MODEL_TB_SIZES(16384, 8192),
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MODEL_RATES(2, 4, 32)),
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VALHALL_MODEL(0xac04, 2, "G310v3", "TVAx", MODEL_ANISO(ALL), MODEL_TB_SIZES(16384, 8192),
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VALHALL_MODEL(PROD_ID(10, 12, 4), 2, "G310v3", "TVAx", MODEL_ANISO(ALL), MODEL_TB_SIZES(16384, 8192),
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MODEL_RATES(4, 4, 48)),
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VALHALL_MODEL(0xac04, 3, "G310v4", "TVAx", MODEL_ANISO(ALL), MODEL_TB_SIZES(32768, 16384),
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VALHALL_MODEL(PROD_ID(10, 12, 4), 3, "G310v4", "TVAx", MODEL_ANISO(ALL), MODEL_TB_SIZES(32768, 16384),
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MODEL_RATES(4, 8, 48)),
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VALHALL_MODEL(0xac04, 4, "G310v5", "TVAx", MODEL_ANISO(ALL), MODEL_TB_SIZES(32768, 16384),
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VALHALL_MODEL(PROD_ID(10, 12, 4), 4, "G310v5", "TVAx", MODEL_ANISO(ALL), MODEL_TB_SIZES(32768, 16384),
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MODEL_RATES(4, 8, 64)),
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FIFTHGEN_MODEL(0xc800, 4, "G720", "TTIx", MODEL_ANISO(ALL), MODEL_TB_SIZES(65536, 32768),
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FIFTHGEN_MODEL(PROD_ID(12, 8, 0), 4, "G720", "TTIx", MODEL_ANISO(ALL), MODEL_TB_SIZES(65536, 32768),
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MODEL_RATES(4, 8, 128)),
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FIFTHGEN_MODEL(0xd800, 4, "G725", "TKRx", MODEL_ANISO(ALL), MODEL_TB_SIZES(65536, 65536),
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FIFTHGEN_MODEL(PROD_ID(13, 8, 0), 4, "G725", "TKRx", MODEL_ANISO(ALL), MODEL_TB_SIZES(65536, 65536),
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MODEL_RATES(4, 8, 128)),
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};
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/* clang-format on */
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@ -122,6 +123,18 @@ const struct pan_model pan_model_list[] = {
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#undef MODEL_RATES
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#undef MODEL_QUIRKS
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static uint32_t
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get_prod_id(uint32_t gpu_id)
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{
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unsigned arch = pan_arch(gpu_id);
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if (arch < 6)
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return MIDGARD_PRODUCT_ID(gpu_id);
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return PROD_ID(PAN_ARCH_MAJOR(gpu_id), PAN_ARCH_MINOR(gpu_id),
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PAN_PRODUCT_MAJOR(gpu_id));
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}
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#undef PROD_ID
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/*
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* Look up a supported model by its GPU ID, or return NULL if the model is not
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* supported at this time.
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@ -129,9 +142,8 @@ const struct pan_model pan_model_list[] = {
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const struct pan_model *
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pan_get_model(uint32_t gpu_id, uint32_t gpu_variant)
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{
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uint32_t gpu_prod_id = get_prod_id(gpu_id);
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for (unsigned i = 0; i < ARRAY_SIZE(pan_model_list); ++i) {
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uint32_t gpu_prod_id = gpu_id & pan_model_list[i].gpu_prod_id_mask;
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if (pan_model_list[i].gpu_prod_id == gpu_prod_id &&
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pan_model_list[i].gpu_variant == gpu_variant)
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return &pan_model_list[i];
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@ -1,5 +1,6 @@
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/*
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* Copyright (C) 2019 Collabora, Ltd.
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* Copyright (C) 2026 Arm Ltd.
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* SPDX-License-Identifier: MIT
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*/
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@ -21,21 +22,21 @@ struct pan_tiler_features {
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unsigned max_levels;
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};
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#define ARCH_MAJOR BITFIELD_RANGE(28, 4)
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#define ARCH_MINOR BITFIELD_RANGE(24, 4)
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#define ARCH_REV BITFIELD_RANGE(20, 4)
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#define PRODUCT_MAJOR BITFIELD_RANGE(16, 4)
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#define VERSION_MAJOR BITFIELD_RANGE(12, 4)
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#define VERSION_MINOR BITFIELD_RANGE(4, 8)
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#define VERSION_STATUS BITFIELD_RANGE(0, 4)
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#define MIDGARD_PRODUCT_ID(x) (((x) & BITFIELD_RANGE(16, 16)) >> 16)
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#define PAN_ARCH_MAJOR(x) (((x) & BITFIELD_RANGE(28, 4)) >> 28)
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#define PAN_ARCH_MINOR(x) (((x) & BITFIELD_RANGE(24, 4)) >> 24)
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#define PAN_ARCH_REV(x) (((x) & BITFIELD_RANGE(20, 4)) >> 20)
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#define PAN_PRODUCT_MAJOR(x) (((x) & BITFIELD_RANGE(16, 4)) >> 16)
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#define PAN_VERSION_MAJOR(x) (((x) & BITFIELD_RANGE(12, 4)) >> 12)
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#define PAN_VERSION_MINOR(x) (((x) & BITFIELD_RANGE(4, 8)) >> 4)
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#define PAN_VERSION_STATUS(x) ((x) & BITFIELD_RANGE(0, 4))
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struct pan_model {
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/* GPU product ID */
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uint32_t gpu_prod_id;
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/* Mask to apply to the GPU ID to get a product ID. */
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uint32_t gpu_prod_id_mask;
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/* GPU variant. */
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uint32_t gpu_variant;
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@ -87,7 +88,7 @@ const struct pan_model *pan_get_model(uint32_t gpu_id, uint32_t gpu_variant);
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static inline unsigned
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pan_arch(unsigned gpu_id)
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{
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switch (gpu_id >> 16) {
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switch (MIDGARD_PRODUCT_ID(gpu_id)) {
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case 0x600:
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case 0x620:
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case 0x720:
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@ -99,7 +100,7 @@ pan_arch(unsigned gpu_id)
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case 0x880:
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return 5;
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default:
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return gpu_id >> 28;
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return PAN_ARCH_MAJOR(gpu_id);
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}
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}
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