From f181cc5bcad71a498ad0ac80091a6e257404877d Mon Sep 17 00:00:00 2001 From: Lars-Ivar Hesselberg Simonsen Date: Tue, 24 Mar 2026 15:03:20 +0100 Subject: [PATCH] pan/model: Redo gpu_prod_id in the model The current implementation is a bit awkward and becomes tricky when adding support for 64 bit gpu_ids. Rather than keeping a mask of bits in gpu_id to compare with the stored gpu_prod_id value, rely on macro functions for fetching the information required from gpu_id and creating the comparison value. Reviewed-by: Aksel Hjerpbakk Reviewed-by: Eric R. Smith Part-of: --- src/panfrost/model/pan_model.c | 70 ++++++++++++++++++++-------------- src/panfrost/model/pan_model.h | 25 ++++++------ 2 files changed, 54 insertions(+), 41 deletions(-) diff --git a/src/panfrost/model/pan_model.c b/src/panfrost/model/pan_model.c index 553b30e1c43..1e173be4381 100644 --- a/src/panfrost/model/pan_model.c +++ b/src/panfrost/model/pan_model.c @@ -1,5 +1,6 @@ /* * Copyright (C) 2019 Collabora, Ltd. + * Copyright (C) 2026 Arm Ltd. * SPDX-License-Identifier: MIT */ @@ -14,11 +15,9 @@ #define GPU_REV_R0P3 GPU_REV(0, 3) #define GPU_REV_R1P1 GPU_REV(1, 1) -#define MODEL(gpu_prod_id_, gpu_prod_id_mask_, gpu_variant_, shortname, \ - counters, ...) \ +#define MODEL(gpu_prod_id_, gpu_variant_, shortname, counters, ...) \ { \ .gpu_prod_id = gpu_prod_id_, \ - .gpu_prod_id_mask = gpu_prod_id_mask_, \ .gpu_variant = gpu_variant_, \ .name = "Mali-" shortname, \ .performance_counters = counters, \ @@ -26,19 +25,21 @@ } #define MIDGARD_MODEL(gpu_prod_id, shortname, counters, ...) \ - MODEL(gpu_prod_id << 16, 0xffff0000, 0, shortname, counters, ##__VA_ARGS__) + MODEL(gpu_prod_id, 0, shortname, counters, ##__VA_ARGS__) + +/* Assume 8 bits per field. This ensures the prod_id is always greater than + * Midgard's. */ +#define PROD_ID(arch_major, arch_minor, prod_major) \ + (((arch_major) << 16) | ((arch_minor) << 8) | (prod_major)) #define BIFROST_MODEL(gpu_prod_id, shortname, counters, ...) \ - MODEL(gpu_prod_id << 16, ARCH_MAJOR | ARCH_MINOR | PRODUCT_MAJOR, 0, \ - shortname, counters, ##__VA_ARGS__) + MODEL(gpu_prod_id, 0, shortname, counters, ##__VA_ARGS__) #define VALHALL_MODEL(gpu_prod_id, gpu_variant, shortname, counters, ...) \ - MODEL(gpu_prod_id << 16, ARCH_MAJOR | ARCH_MINOR | PRODUCT_MAJOR, \ - gpu_variant, shortname, counters, ##__VA_ARGS__) + MODEL(gpu_prod_id, gpu_variant, shortname, counters, ##__VA_ARGS__) #define FIFTHGEN_MODEL(gpu_prod_id, gpu_variant, shortname, counters, ...) \ - MODEL(gpu_prod_id << 16, ARCH_MAJOR | ARCH_MINOR | PRODUCT_MAJOR, \ - gpu_variant, shortname, counters, ##__VA_ARGS__) + MODEL(gpu_prod_id, gpu_variant, shortname, counters, ##__VA_ARGS__) #define MODEL_ANISO(rev) .min_rev_anisotropic = GPU_REV_##rev @@ -73,34 +74,34 @@ const struct pan_model pan_model_list[] = { MIDGARD_MODEL(0x860, "T860", "T86x", MODEL_ANISO(NONE), MODEL_TB_SIZES( 8192, 8192)), MIDGARD_MODEL(0x880, "T880", "T88x", MODEL_ANISO(NONE), MODEL_TB_SIZES( 8192, 8192)), - BIFROST_MODEL(0x6000, "G71", "TMIx", MODEL_ANISO(NONE), MODEL_TB_SIZES( 4096, 4096)), - BIFROST_MODEL(0x6201, "G72", "THEx", MODEL_ANISO(R0P3), MODEL_TB_SIZES( 8192, 4096)), - BIFROST_MODEL(0x7000, "G51", "TSIx", MODEL_ANISO(R1P1), MODEL_TB_SIZES( 8192, 8192)), - BIFROST_MODEL(0x7003, "G31", "TDVx", MODEL_ANISO(ALL), MODEL_TB_SIZES( 8192, 8192)), - BIFROST_MODEL(0x7201, "G76", "TNOx", MODEL_ANISO(ALL), MODEL_TB_SIZES(16384, 8192)), - BIFROST_MODEL(0x7202, "G52", "TGOx", MODEL_ANISO(ALL), MODEL_TB_SIZES(16384, 8192)), - BIFROST_MODEL(0x7402, "G52 r1", "TGOx", MODEL_ANISO(ALL), MODEL_TB_SIZES( 8192, 8192)), + BIFROST_MODEL(PROD_ID(6, 0, 0), "G71", "TMIx", MODEL_ANISO(NONE), MODEL_TB_SIZES( 4096, 4096)), + BIFROST_MODEL(PROD_ID(6, 2, 1), "G72", "THEx", MODEL_ANISO(R0P3), MODEL_TB_SIZES( 8192, 4096)), + BIFROST_MODEL(PROD_ID(7, 0, 0), "G51", "TSIx", MODEL_ANISO(R1P1), MODEL_TB_SIZES( 8192, 8192)), + BIFROST_MODEL(PROD_ID(7, 0, 3), "G31", "TDVx", MODEL_ANISO(ALL), MODEL_TB_SIZES( 8192, 8192)), + BIFROST_MODEL(PROD_ID(7, 2, 1), "G76", "TNOx", MODEL_ANISO(ALL), MODEL_TB_SIZES(16384, 8192)), + BIFROST_MODEL(PROD_ID(7, 2, 2), "G52", "TGOx", MODEL_ANISO(ALL), MODEL_TB_SIZES(16384, 8192)), + BIFROST_MODEL(PROD_ID(7, 4, 2), "G52 r1", "TGOx", MODEL_ANISO(ALL), MODEL_TB_SIZES( 8192, 8192)), - VALHALL_MODEL(0x9001, 0, "G57", "TNAx", MODEL_ANISO(ALL), MODEL_TB_SIZES(16384, 8192), + VALHALL_MODEL(PROD_ID(9, 0, 1), 0, "G57", "TNAx", MODEL_ANISO(ALL), MODEL_TB_SIZES(16384, 8192), MODEL_RATES(2, 4, 32)), - VALHALL_MODEL(0x9003, 0, "G57", "TNAx", MODEL_ANISO(ALL), MODEL_TB_SIZES(16384, 8192), + VALHALL_MODEL(PROD_ID(9, 0, 3), 0, "G57", "TNAx", MODEL_ANISO(ALL), MODEL_TB_SIZES(16384, 8192), MODEL_RATES(2, 4, 32)), - VALHALL_MODEL(0xa807, 0, "G610", "TVIx", MODEL_ANISO(ALL), MODEL_TB_SIZES(32768, 16384), + VALHALL_MODEL(PROD_ID(10, 8, 7), 0, "G610", "TVIx", MODEL_ANISO(ALL), MODEL_TB_SIZES(32768, 16384), MODEL_RATES(4, 8, 64)), - VALHALL_MODEL(0xac04, 0, "G310v1", "TVAx", MODEL_ANISO(ALL), MODEL_TB_SIZES(16384, 8192), + VALHALL_MODEL(PROD_ID(10, 12, 4), 0, "G310v1", "TVAx", MODEL_ANISO(ALL), MODEL_TB_SIZES(16384, 8192), MODEL_RATES(2, 2, 16)), - VALHALL_MODEL(0xac04, 1, "G310v2", "TVAx", MODEL_ANISO(ALL), MODEL_TB_SIZES(16384, 8192), + VALHALL_MODEL(PROD_ID(10, 12, 4), 1, "G310v2", "TVAx", MODEL_ANISO(ALL), MODEL_TB_SIZES(16384, 8192), MODEL_RATES(2, 4, 32)), - VALHALL_MODEL(0xac04, 2, "G310v3", "TVAx", MODEL_ANISO(ALL), MODEL_TB_SIZES(16384, 8192), + VALHALL_MODEL(PROD_ID(10, 12, 4), 2, "G310v3", "TVAx", MODEL_ANISO(ALL), MODEL_TB_SIZES(16384, 8192), MODEL_RATES(4, 4, 48)), - VALHALL_MODEL(0xac04, 3, "G310v4", "TVAx", MODEL_ANISO(ALL), MODEL_TB_SIZES(32768, 16384), + VALHALL_MODEL(PROD_ID(10, 12, 4), 3, "G310v4", "TVAx", MODEL_ANISO(ALL), MODEL_TB_SIZES(32768, 16384), MODEL_RATES(4, 8, 48)), - VALHALL_MODEL(0xac04, 4, "G310v5", "TVAx", MODEL_ANISO(ALL), MODEL_TB_SIZES(32768, 16384), + VALHALL_MODEL(PROD_ID(10, 12, 4), 4, "G310v5", "TVAx", MODEL_ANISO(ALL), MODEL_TB_SIZES(32768, 16384), MODEL_RATES(4, 8, 64)), - FIFTHGEN_MODEL(0xc800, 4, "G720", "TTIx", MODEL_ANISO(ALL), MODEL_TB_SIZES(65536, 32768), + FIFTHGEN_MODEL(PROD_ID(12, 8, 0), 4, "G720", "TTIx", MODEL_ANISO(ALL), MODEL_TB_SIZES(65536, 32768), MODEL_RATES(4, 8, 128)), - FIFTHGEN_MODEL(0xd800, 4, "G725", "TKRx", MODEL_ANISO(ALL), MODEL_TB_SIZES(65536, 65536), + FIFTHGEN_MODEL(PROD_ID(13, 8, 0), 4, "G725", "TKRx", MODEL_ANISO(ALL), MODEL_TB_SIZES(65536, 65536), MODEL_RATES(4, 8, 128)), }; /* clang-format on */ @@ -122,6 +123,18 @@ const struct pan_model pan_model_list[] = { #undef MODEL_RATES #undef MODEL_QUIRKS +static uint32_t +get_prod_id(uint32_t gpu_id) +{ + unsigned arch = pan_arch(gpu_id); + if (arch < 6) + return MIDGARD_PRODUCT_ID(gpu_id); + return PROD_ID(PAN_ARCH_MAJOR(gpu_id), PAN_ARCH_MINOR(gpu_id), + PAN_PRODUCT_MAJOR(gpu_id)); +} + +#undef PROD_ID + /* * Look up a supported model by its GPU ID, or return NULL if the model is not * supported at this time. @@ -129,9 +142,8 @@ const struct pan_model pan_model_list[] = { const struct pan_model * pan_get_model(uint32_t gpu_id, uint32_t gpu_variant) { + uint32_t gpu_prod_id = get_prod_id(gpu_id); for (unsigned i = 0; i < ARRAY_SIZE(pan_model_list); ++i) { - uint32_t gpu_prod_id = gpu_id & pan_model_list[i].gpu_prod_id_mask; - if (pan_model_list[i].gpu_prod_id == gpu_prod_id && pan_model_list[i].gpu_variant == gpu_variant) return &pan_model_list[i]; diff --git a/src/panfrost/model/pan_model.h b/src/panfrost/model/pan_model.h index f0e279891f3..27b7fe8d21c 100644 --- a/src/panfrost/model/pan_model.h +++ b/src/panfrost/model/pan_model.h @@ -1,5 +1,6 @@ /* * Copyright (C) 2019 Collabora, Ltd. + * Copyright (C) 2026 Arm Ltd. * SPDX-License-Identifier: MIT */ @@ -21,21 +22,21 @@ struct pan_tiler_features { unsigned max_levels; }; -#define ARCH_MAJOR BITFIELD_RANGE(28, 4) -#define ARCH_MINOR BITFIELD_RANGE(24, 4) -#define ARCH_REV BITFIELD_RANGE(20, 4) -#define PRODUCT_MAJOR BITFIELD_RANGE(16, 4) -#define VERSION_MAJOR BITFIELD_RANGE(12, 4) -#define VERSION_MINOR BITFIELD_RANGE(4, 8) -#define VERSION_STATUS BITFIELD_RANGE(0, 4) +#define MIDGARD_PRODUCT_ID(x) (((x) & BITFIELD_RANGE(16, 16)) >> 16) + +#define PAN_ARCH_MAJOR(x) (((x) & BITFIELD_RANGE(28, 4)) >> 28) +#define PAN_ARCH_MINOR(x) (((x) & BITFIELD_RANGE(24, 4)) >> 24) +#define PAN_ARCH_REV(x) (((x) & BITFIELD_RANGE(20, 4)) >> 20) +#define PAN_PRODUCT_MAJOR(x) (((x) & BITFIELD_RANGE(16, 4)) >> 16) + +#define PAN_VERSION_MAJOR(x) (((x) & BITFIELD_RANGE(12, 4)) >> 12) +#define PAN_VERSION_MINOR(x) (((x) & BITFIELD_RANGE(4, 8)) >> 4) +#define PAN_VERSION_STATUS(x) ((x) & BITFIELD_RANGE(0, 4)) struct pan_model { /* GPU product ID */ uint32_t gpu_prod_id; - /* Mask to apply to the GPU ID to get a product ID. */ - uint32_t gpu_prod_id_mask; - /* GPU variant. */ uint32_t gpu_variant; @@ -87,7 +88,7 @@ const struct pan_model *pan_get_model(uint32_t gpu_id, uint32_t gpu_variant); static inline unsigned pan_arch(unsigned gpu_id) { - switch (gpu_id >> 16) { + switch (MIDGARD_PRODUCT_ID(gpu_id)) { case 0x600: case 0x620: case 0x720: @@ -99,7 +100,7 @@ pan_arch(unsigned gpu_id) case 0x880: return 5; default: - return gpu_id >> 28; + return PAN_ARCH_MAJOR(gpu_id); } }