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intel/xehp: Implement XeHP workaround Wa_14013910100.

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XeHP platforms require the invalidation of the instruction cache after
a STATE_BASE_ADDRESS change due to a hardware bug potentially leading
to instruction cache pollution.  Note that the workaround text says
it's applicable "DG2 128/256/512-A/B", however it's also marked as
permanent and not confirmed to be fixed in any specific steping, so we
apply it to all Gfx12HP platforms.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14278>
This commit is contained in:
Francisco Jerez 2021-06-18 19:39:08 -07:00 • committed by Marge Bot
parent b550b3c89c
commit eeb3f4594d
2 changed files with 18 additions and 1 deletions
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10
src/gallium/drivers/iris/iris_state.c
View file

@ -449,12 +449,20 @@ flush_after_state_base_change(struct iris_batch *batch)
* sufficient. The theory here is that all of the sampling/rendering
* units cache the binding table in the texture cache. However, we have
* yet to be able to actually confirm this.
*
* Wa_14013910100:
*
* "DG2 128/256/512-A/B: S/W must program STATE_BASE_ADDRESS command twice
* or program pipe control with Instruction cache invalidate post
* STATE_BASE_ADDRESS command"
*/
iris_emit_end_of_pipe_sync(batch,
"change STATE_BASE_ADDRESS (invalidates)",
PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
PIPE_CONTROL_CONST_CACHE_INVALIDATE |
PIPE_CONTROL_STATE_CACHE_INVALIDATE);
PIPE_CONTROL_STATE_CACHE_INVALIDATE |
(GFX_VERx10 != 125 ? 0 :
PIPE_CONTROL_INSTRUCTION_INVALIDATE));
}
static void

9
src/intel/vulkan/genX_cmd_buffer.c
View file

@ -263,11 +263,20 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
* sufficient. The theory here is that all of the sampling/rendering
* units cache the binding table in the texture cache. However, we have
* yet to be able to actually confirm this.
*
* Wa_14013910100:
*
* "DG2 128/256/512-A/B: S/W must program STATE_BASE_ADDRESS command twice
* or program pipe control with Instruction cache invalidate post
* STATE_BASE_ADDRESS command"
*/
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
pc.TextureCacheInvalidationEnable = true;
pc.ConstantCacheInvalidationEnable = true;
pc.StateCacheInvalidationEnable = true;
#if GFX_VERx10 == 125
pc.InstructionCacheInvalidateEnable = true;
#endif
anv_debug_dump_pc(pc);
}
}