From eeb3f4594d5acc40c1febf22f97ddb51517a0c88 Mon Sep 17 00:00:00 2001 From: Francisco Jerez Date: Fri, 18 Jun 2021 19:39:08 -0700 Subject: [PATCH] intel/xehp: Implement XeHP workaround Wa_14013910100. XeHP platforms require the invalidation of the instruction cache after a STATE_BASE_ADDRESS change due to a hardware bug potentially leading to instruction cache pollution. Note that the workaround text says it's applicable "DG2 128/256/512-A/B", however it's also marked as permanent and not confirmed to be fixed in any specific steping, so we apply it to all Gfx12HP platforms. Reviewed-by: Lionel Landwerlin Reviewed-by: Rohan Garg Part-of: --- src/gallium/drivers/iris/iris_state.c | 10 +++++++++- src/intel/vulkan/genX_cmd_buffer.c | 9 +++++++++ 2 files changed, 18 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 29e3511844c..f4e18db5a21 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -449,12 +449,20 @@ flush_after_state_base_change(struct iris_batch *batch) * sufficient. The theory here is that all of the sampling/rendering * units cache the binding table in the texture cache. However, we have * yet to be able to actually confirm this. + * + * Wa_14013910100: + * + * "DG2 128/256/512-A/B: S/W must program STATE_BASE_ADDRESS command twice + * or program pipe control with Instruction cache invalidate post + * STATE_BASE_ADDRESS command" */ iris_emit_end_of_pipe_sync(batch, "change STATE_BASE_ADDRESS (invalidates)", PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | PIPE_CONTROL_CONST_CACHE_INVALIDATE | - PIPE_CONTROL_STATE_CACHE_INVALIDATE); + PIPE_CONTROL_STATE_CACHE_INVALIDATE | + (GFX_VERx10 != 125 ? 0 : + PIPE_CONTROL_INSTRUCTION_INVALIDATE)); } static void diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 5c097e65c36..a74ff8229b8 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -263,11 +263,20 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer) * sufficient. The theory here is that all of the sampling/rendering * units cache the binding table in the texture cache. However, we have * yet to be able to actually confirm this. + * + * Wa_14013910100: + * + * "DG2 128/256/512-A/B: S/W must program STATE_BASE_ADDRESS command twice + * or program pipe control with Instruction cache invalidate post + * STATE_BASE_ADDRESS command" */ anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { pc.TextureCacheInvalidationEnable = true; pc.ConstantCacheInvalidationEnable = true; pc.StateCacheInvalidationEnable = true; +#if GFX_VERx10 == 125 + pc.InstructionCacheInvalidateEnable = true; +#endif anv_debug_dump_pc(pc); } }