diff --git a/src/freedreno/registers/adreno/adreno_pm4.xml b/src/freedreno/registers/adreno/adreno_pm4.xml
index ba46e9d5ae4..7ca31f15d6e 100644
--- a/src/freedreno/registers/adreno/adreno_pm4.xml
+++ b/src/freedreno/registers/adreno/adreno_pm4.xml
@@ -6,103 +6,103 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
-
-
-
-
+
+
+
+
Flushes dirty data from UCHE, and also writes a GPU timestamp to
the address if one is provided.
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
-
-
-
-
-
+
+
+
+
+
If A6XX_RB_SAMPLE_COUNTER_CNTL.copy is true, writes OQ Z passed
sample counts to RB_SAMPLE_COUNTER_BASE. This writes to main
memory, skipping UCHE.
-
-
+
+
Writes the GPU timestamp to the address that follows, once RB
access and flushes are complete.
-
+
-
-
-
-
+
+
+
+
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
Invalidates depth attachment data from the CCU. We assume this
happens in the last stage.
-
+
Invalidates color attachment data from the CCU. We assume this
happens in the last stage.
-
+
Flushes the small cache used by CP_EVENT_WRITE::BLIT (which,
along with its registers, would be better named RESOLVE).
-
+
Flushes depth attachment data from the CCU. We assume this
happens in the last stage.
-
+
Flushes color attachment data from the CCU. We assume this
happens in the last stage.
-
+
2D blit to resolve GMEM to system memory (skipping CCU) at the
end of a render pass. Compare to CP_BLIT's BLIT_OP_SCALE for
more general blitting.
-
+
Flip between the primary and secondary LRZ buffers. This is used
for concurrent binning, so that BV can write to one buffer while
BR reads from the other.
-
+
Clears based on GRAS_LRZ_CNTL configuration, could clear
@@ -115,44 +115,44 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
CUR_DIR_UNSET = 0x3
Clear of direction means setting the direction to CUR_DIR_UNSET.
-
+
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
Invalidates UCHE.
-
+
-
+
Doesn't seem to do anything
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
-
-
+
+