From ebc5116e707a813deec34b0f55d304daefe80072 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Tue, 30 Jul 2024 16:10:45 -0400 Subject: [PATCH] radeonsi: ensure TC_L2_dirty is set if we don't sync after internal SSBO blits There was a case where if we don't sync, we wouldn't set TC_L2_dirty either, which could cause problems later. Fixes: f703dfd1bb8 - radeonsi: add gfx12 Reviewed-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/gallium/drivers/radeonsi/si_compute_blit.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_compute_blit.c b/src/gallium/drivers/radeonsi/si_compute_blit.c index 783ef9a8dbe..0336d7ceefe 100644 --- a/src/gallium/drivers/radeonsi/si_compute_blit.c +++ b/src/gallium/drivers/radeonsi/si_compute_blit.c @@ -187,11 +187,9 @@ void si_launch_grid_internal_ssbos(struct si_context *sctx, struct pipe_grid_inf si_launch_grid_internal(sctx, info, shader, flags); /* Do cache flushing at the end. */ - if (get_cache_policy(sctx, coher, 0) == L2_BYPASS) { - if (flags & SI_OP_SYNC_AFTER) { - sctx->flags |= SI_CONTEXT_WB_L2; - si_mark_atom_dirty(sctx, &sctx->atoms.s.cache_flush); - } + if (flags & SI_OP_SYNC_AFTER && get_cache_policy(sctx, coher, 0) == L2_BYPASS) { + sctx->flags |= SI_CONTEXT_WB_L2; + si_mark_atom_dirty(sctx, &sctx->atoms.s.cache_flush); } else { while (writeable_bitmask) si_resource(buffers[u_bit_scan(&writeable_bitmask)].buffer)->TC_L2_dirty = true;