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GEM: Remove already-disabled PIPE_CONTROL command.

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This existed to get the icache flushed.  However, GEM handles this for us
now for sure, and we had disabled it prematurely anyway.
This commit is contained in:
Eric Anholt 2008-05-07 14:01:03 -07:00
parent ab50ddaa91
commit ead798eb10
2 changed files with 0 additions and 35 deletions
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34
src/mesa/drivers/dri/i965/brw_misc_state.c
View file

@ -383,40 +383,6 @@ const struct brw_tracked_state brw_line_stipple = {
};
/***********************************************************************
* Misc constant state packets
*/
static void upload_pipe_control(struct brw_context *brw)
{
struct brw_pipe_control pc;
return;
memset(&pc, 0, sizeof(pc));
pc.header.opcode = CMD_PIPE_CONTROL;
pc.header.length = sizeof(pc)/4 - 2;
pc.header.post_sync_operation = PIPE_CONTROL_NOWRITE;
pc.header.instruction_state_cache_flush_enable = 1;
pc.bits1.dest_addr_type = PIPE_CONTROL_GTTWRITE_GLOBAL;
BRW_BATCH_STRUCT(brw, &pc);
}
const struct brw_tracked_state brw_pipe_control = {
.dirty = {
.mesa = 0,
.brw = BRW_NEW_BATCH,
.cache = 0
},
.emit = upload_pipe_control
};
/***********************************************************************
* Misc invarient state packets
*/

1
src/mesa/drivers/dri/i965/brw_state_upload.c
View file

@ -80,7 +80,6 @@ const struct brw_tracked_state *atoms[] =
*/
&brw_invarient_state,
&brw_state_base_address,
&brw_pipe_control,
&brw_binding_table_pointers,
&brw_blend_constant_color,