fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-02-14 04:40:28 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

GEM: Make dri_emit_reloc take GEM domain flags instead of TTM flags.

Browse source 
The GEM flags are much more descriptive for what we need.  Since this makes
bufmgr_fake rather device-specific, move it to the intel common directory.
We've wanted to do device-specific stuff to it before.
This commit is contained in:
Eric Anholt 2008-05-07 13:51:29 -07:00
parent 8b2a7f08bc
commit ab50ddaa91
27 changed files with 186 additions and 115 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
src/mesa/drivers/dri/Makefile.template
View file

@ -12,8 +12,7 @@ COMMON_SOURCES = \
../common/drirenderbuffer.c
COMMON_BM_SOURCES = \
../common/dri_bufmgr.c \
../common/dri_bufmgr_fake.c
../common/dri_bufmgr.c
ifeq ($(WINDOW_SYSTEM),dri)

8
src/mesa/drivers/dri/common/dri_bufmgr.c
View file

@ -121,10 +121,12 @@ dri_bufmgr_destroy(dri_bufmgr *bufmgr)
}
int dri_emit_reloc(dri_bo *reloc_buf, uint64_t flags, GLuint delta,
GLuint offset, dri_bo *target_buf)
int dri_emit_reloc(dri_bo *reloc_buf,
uint32_t read_domains, uint32_t write_domain,
uint32_t delta, uint32_t offset, dri_bo *target_buf)
{
return reloc_buf->bufmgr->emit_reloc(reloc_buf, flags, delta, offset, target_buf);
return reloc_buf->bufmgr->emit_reloc(reloc_buf, read_domains, write_domain,
delta, offset, target_buf);
}
void *dri_process_relocs(dri_bo *batch_buf)

21
src/mesa/drivers/dri/common/dri_bufmgr.h
View file

@ -135,8 +135,9 @@ struct _dri_bufmgr {
* \param target Buffer whose offset should be written into the relocation
* entry.
*/
int (*emit_reloc)(dri_bo *reloc_buf, uint64_t flags, GLuint delta,
GLuint offset, dri_bo *target);
int (*emit_reloc)(dri_bo *reloc_buf,
uint32_t read_domains, uint32_t write_domain,
uint32_t delta, uint32_t offset, dri_bo *target);
/**
* Processes the relocations, either in userland or by converting the list
@ -174,22 +175,12 @@ void dri_bo_subdata(dri_bo *bo, unsigned long offset,
void dri_bo_get_subdata(dri_bo *bo, unsigned long offset,
unsigned long size, void *data);
void dri_bufmgr_fake_contended_lock_take(dri_bufmgr *bufmgr);
dri_bufmgr *dri_bufmgr_fake_init(unsigned long low_offset, void *low_virtual,
unsigned long size,
unsigned int (*fence_emit)(void *private),
int (*fence_wait)(void *private,
unsigned int cookie),
void *driver_priv);
void dri_bufmgr_set_debug(dri_bufmgr *bufmgr, GLboolean enable_debug);
void dri_bo_fake_disable_backing_store(dri_bo *bo,
void (*invalidate_cb)(dri_bo *bo,
void *ptr),
void *ptr);
void dri_bufmgr_destroy(dri_bufmgr *bufmgr);
int dri_emit_reloc(dri_bo *reloc_buf, uint64_t flags, GLuint delta,
GLuint offset, dri_bo *target_buf);
int dri_emit_reloc(dri_bo *reloc_buf,
uint32_t read_domains, uint32_t write_domain,
uint32_t delta, uint32_t offset, dri_bo *target_buf);
void *dri_process_relocs(dri_bo *batch_buf);
void dri_post_process_relocs(dri_bo *batch_buf);
void dri_post_submit(dri_bo *batch_buf);

1
src/mesa/drivers/dri/i915/Makefile
View file

@ -54,6 +54,7 @@ DRIVER_SOURCES = \
intel_tris.c \
intel_fbo.c \
intel_depthstencil.c \
intel_bufmgr_fake.c \
intel_bufmgr_gem.c
C_SOURCES = \

6
src/mesa/drivers/dri/i915/i830_vtbl.c
View file

@ -490,14 +490,14 @@ i830_emit_state(struct intel_context *intel)
OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR0]);
OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR1]);
OUT_RELOC(state->draw_region->buffer,
DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
DRM_GEM_DOMAIN_I915_RENDER, DRM_GEM_DOMAIN_I915_RENDER,
state->draw_region->draw_offset);
if (state->depth_region) {
OUT_BATCH(state->Buffer[I830_DESTREG_DBUFADDR0]);
OUT_BATCH(state->Buffer[I830_DESTREG_DBUFADDR1]);
OUT_RELOC(state->depth_region->buffer,
DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
DRM_GEM_DOMAIN_I915_RENDER, DRM_GEM_DOMAIN_I915_RENDER,
state->depth_region->draw_offset);
}
@ -524,7 +524,7 @@ i830_emit_state(struct intel_context *intel)
if (state->tex_buffer[i]) {
OUT_RELOC(state->tex_buffer[i],
DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
DRM_GEM_DOMAIN_I915_SAMPLER, 0,
state->tex_offset[i] | TM0S0_USE_FENCE);
}
else if (state == &i830->meta) {

6
src/mesa/drivers/dri/i915/i915_vtbl.c
View file

@ -377,14 +377,14 @@ i915_emit_state(struct intel_context *intel)
OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR0]);
OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR1]);
OUT_RELOC(state->draw_region->buffer,
DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
DRM_GEM_DOMAIN_I915_RENDER, DRM_GEM_DOMAIN_I915_RENDER,
state->draw_region->draw_offset);
if (state->depth_region) {
OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR0]);
OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR1]);
OUT_RELOC(state->depth_region->buffer,
DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
DRM_GEM_DOMAIN_I915_RENDER, DRM_GEM_DOMAIN_I915_RENDER,
state->depth_region->draw_offset);
}
@ -427,7 +427,7 @@ i915_emit_state(struct intel_context *intel)
if (state->tex_buffer[i]) {
OUT_RELOC(state->tex_buffer[i],
DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
DRM_GEM_DOMAIN_I915_SAMPLER, 0,
state->tex_offset[i]);
}
else if (state == &i915->meta) {

1
src/mesa/drivers/dri/i915/intel_bufmgr_fake.c Symbolic link
View file

@ -0,0 +1 @@
../intel/intel_bufmgr_fake.c

1
src/mesa/drivers/dri/i965/Makefile
View file

@ -9,6 +9,7 @@ DRIVER_SOURCES = \
intel_blit.c \
intel_buffer_objects.c \
intel_buffers.c \
intel_bufmgr_fake.c \
intel_bufmgr_gem.c \
intel_context.c \
intel_decode.c \

3
src/mesa/drivers/dri/i965/brw_cc.c
View file

@ -257,7 +257,8 @@ cc_unit_create_from_key(struct brw_context *brw, struct brw_cc_unit_key *key)
/* Emit CC viewport relocation */
dri_emit_reloc(bo,
DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
DRM_GEM_DOMAIN_I915_INSTRUCTION,
0,
0,
offsetof(struct brw_cc_unit_state, cc4),
brw->cc.vp_bo);

3
src/mesa/drivers/dri/i965/brw_clip_state.c
View file

@ -120,7 +120,8 @@ clip_unit_create_from_key(struct brw_context *brw,
/* Emit clip program relocation */
assert(brw->clip.prog_bo);
dri_emit_reloc(bo,
DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
DRM_GEM_DOMAIN_I915_INSTRUCTION,
0,
clip.thread0.grf_reg_count << 1,
offsetof(struct brw_clip_unit_state, thread0),
brw->clip.prog_bo);

3
src/mesa/drivers/dri/i965/brw_curbe.c
View file

@ -353,7 +353,8 @@ static void emit_constant_buffer(struct brw_context *brw)
OUT_BATCH(0);
} else {
OUT_BATCH((CMD_CONST_BUFFER << 16) | (1 << 8) | (2 - 2));
OUT_RELOC(brw->curbe.curbe_bo, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
OUT_RELOC(brw->curbe.curbe_bo,
DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
(sz - 1) + brw->curbe.curbe_offset);
}
ADVANCE_BATCH();

9
src/mesa/drivers/dri/i965/brw_draw_upload.c
View file

@ -469,7 +469,7 @@ void brw_emit_vertices( struct brw_context *brw,
BRW_VB0_ACCESS_VERTEXDATA |
(input->stride << BRW_VB0_PITCH_SHIFT));
OUT_RELOC(input->bo,
DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
DRM_GEM_DOMAIN_I915_VERTEX, 0,
input->offset);
OUT_BATCH(max_index);
OUT_BATCH(0); /* Instance data step rate */
@ -590,8 +590,11 @@ void brw_emit_indices(struct brw_context *brw,
BEGIN_BATCH(4, IGNORE_CLIPRECTS);
OUT_BATCH( ib.header.dword );
OUT_RELOC( bo, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, offset);
OUT_RELOC( bo, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
OUT_RELOC( bo,
DRM_GEM_DOMAIN_I915_VERTEX, 0,
offset);
OUT_RELOC( bo,
DRM_GEM_DOMAIN_I915_VERTEX, 0,
offset + ib_size);
OUT_BATCH( 0 );
ADVANCE_BATCH();

2
src/mesa/drivers/dri/i965/brw_gs_state.c
View file

@ -107,7 +107,7 @@ gs_unit_create_from_key(struct brw_context *brw, struct brw_gs_unit_key *key)
if (key->prog_active) {
/* Emit GS program relocation */
dri_emit_reloc(bo,
DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
gs.thread0.grf_reg_count << 1,
offsetof(struct brw_gs_unit_state, thread0),
brw->gs.prog_bo);

19
src/mesa/drivers/dri/i965/brw_misc_state.c
View file

@ -88,7 +88,9 @@ static void upload_binding_table_pointers(struct brw_context *brw)
OUT_BATCH(0); /* gs */
OUT_BATCH(0); /* clip */
OUT_BATCH(0); /* sf */
OUT_RELOC(brw->wm.bind_bo, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, 0);
OUT_RELOC(brw->wm.bind_bo,
DRM_GEM_DOMAIN_I915_SAMPLER, 0,
0);
ADVANCE_BATCH();
}
@ -114,18 +116,18 @@ static void upload_pipelined_state_pointers(struct brw_context *brw )
BEGIN_BATCH(7, IGNORE_CLIPRECTS);
OUT_BATCH(CMD_PIPELINED_STATE_POINTERS << 16 | (7 - 2));
OUT_RELOC(brw->vs.state_bo, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, 0);
OUT_RELOC(brw->vs.state_bo, DRM_GEM_DOMAIN_I915_INSTRUCTION, 0, 0);
if (brw->gs.prog_active)
OUT_RELOC(brw->gs.state_bo, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, 1);
OUT_RELOC(brw->gs.state_bo, DRM_GEM_DOMAIN_I915_INSTRUCTION, 0, 1);
else
OUT_BATCH(0);
if (!brw->metaops.active)
OUT_RELOC(brw->clip.state_bo, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, 1);
OUT_RELOC(brw->clip.state_bo, DRM_GEM_DOMAIN_I915_INSTRUCTION, 0, 1);
else
OUT_BATCH(0);
OUT_RELOC(brw->sf.state_bo, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, 0);
OUT_RELOC(brw->wm.state_bo, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, 0);
OUT_RELOC(brw->cc.state_bo, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, 0);
OUT_RELOC(brw->sf.state_bo, DRM_GEM_DOMAIN_I915_INSTRUCTION, 0, 0);
OUT_RELOC(brw->wm.state_bo, DRM_GEM_DOMAIN_I915_INSTRUCTION, 0, 0);
OUT_RELOC(brw->cc.state_bo, DRM_GEM_DOMAIN_I915_INSTRUCTION, 0, 0);
ADVANCE_BATCH();
brw->state.dirty.brw |= BRW_NEW_PSP;
@ -233,7 +235,8 @@ static void emit_depthbuffer(struct brw_context *brw)
(region->tiled << 27) |
(BRW_SURFACE_2D << 29));
OUT_RELOC(region->buffer,
DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE, 0);
DRM_GEM_DOMAIN_I915_RENDER, DRM_GEM_DOMAIN_I915_RENDER,
0);
OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1) |
((region->pitch - 1) << 6) |
((region->height - 1) << 19));

4
src/mesa/drivers/dri/i965/brw_sf_state.c
View file

@ -254,14 +254,14 @@ sf_unit_create_from_key(struct brw_context *brw, struct brw_sf_unit_key *key,
/* Emit SF program relocation */
dri_emit_reloc(bo,
DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
sf.thread0.grf_reg_count << 1,
offsetof(struct brw_sf_unit_state, thread0),
brw->sf.prog_bo);
/* Emit SF viewport relocation */
dri_emit_reloc(bo,
DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
sf.sf5.front_winding | (sf.sf5.viewport_transform << 1),
offsetof(struct brw_sf_unit_state, sf5),
brw->sf.vp_bo);

2
src/mesa/drivers/dri/i965/brw_vs_state.c
View file

@ -116,7 +116,7 @@ vs_unit_create_from_key(struct brw_context *brw, struct brw_vs_unit_key *key)
/* Emit VS program relocation */
dri_emit_reloc(bo,
DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
vs.thread0.grf_reg_count << 1,
offsetof(struct brw_vs_unit_state, thread0),
brw->vs.prog_bo);

2
src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
View file

@ -306,7 +306,7 @@ static int upload_wm_samplers( struct brw_context *brw )
ret |= dri_bufmgr_check_aperture_space(brw->wm.sdc_bo[i]);
dri_emit_reloc(brw->wm.sampler_bo,
DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
0,
i * sizeof(struct brw_sampler_state) +
offsetof(struct brw_sampler_state, ss2),

6
src/mesa/drivers/dri/i965/brw_wm_state.c
View file

@ -200,7 +200,7 @@ wm_unit_create_from_key(struct brw_context *brw, struct brw_wm_unit_key *key,
/* Emit WM program relocation */
dri_emit_reloc(bo,
DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
wm.thread0.grf_reg_count << 1,
offsetof(struct brw_wm_unit_state, thread0),
brw->wm.prog_bo);
@ -208,7 +208,7 @@ wm_unit_create_from_key(struct brw_context *brw, struct brw_wm_unit_key *key,
/* Emit scratch space relocation */
if (key->total_scratch != 0) {
dri_emit_reloc(bo,
DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE,
0, 0,
wm.thread2.per_thread_scratch_space,
offsetof(struct brw_wm_unit_state, thread2),
brw->wm.scratch_buffer);
@ -217,7 +217,7 @@ wm_unit_create_from_key(struct brw_context *brw, struct brw_wm_unit_key *key,
/* Emit sampler state relocation */
if (key->sampler_count != 0) {
dri_emit_reloc(bo,
DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
wm.wm4.stats_enable | (wm.wm4.sampler_count << 2),
offsetof(struct brw_wm_unit_state, wm4),
brw->wm.sampler_bo);

16
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
View file

@ -204,7 +204,7 @@ brw_create_texture_surface( struct brw_context *brw,
/* Emit relocation to surface contents */
dri_emit_reloc(bo,
DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
DRM_GEM_DOMAIN_I915_SAMPLER, 0,
0,
offsetof(struct brw_surface_state, ss1),
key->bo);
@ -337,10 +337,14 @@ brw_update_region_surface(struct brw_context *brw, struct intel_region *region,
&surf, sizeof(surf),
NULL, NULL);
if (region_bo != NULL) {
/* We might sample from it, and we might render to it, so flag
* them both. We might be able to figure out from other state
* a more restrictive relocation to emit.
*/
dri_emit_reloc(brw->wm.surf_bo[unit],
DRM_BO_FLAG_MEM_TT |
DRM_BO_FLAG_READ |
DRM_BO_FLAG_WRITE,
DRM_GEM_DOMAIN_I915_RENDER |
DRM_GEM_DOMAIN_I915_SAMPLER,
DRM_GEM_DOMAIN_I915_RENDER,
0,
offsetof(struct brw_surface_state, ss1),
region_bo);
@ -388,9 +392,7 @@ brw_wm_get_binding_table(struct brw_context *brw)
for (i = 0; i < BRW_WM_MAX_SURF; i++) {
if (brw->wm.surf_bo[i] != NULL) {
dri_emit_reloc(bind_bo,
DRM_BO_FLAG_MEM_TT |
DRM_BO_FLAG_READ |
DRM_BO_FLAG_WRITE,
DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
0,
i * sizeof(GLuint),
brw->wm.surf_bo[i]);

1
src/mesa/drivers/dri/i965/intel_bufmgr_fake.c Symbolic link
View file

@ -0,0 +1 @@
../intel/intel_bufmgr_fake.c

6
src/mesa/drivers/dri/intel/intel_batchbuffer.c
View file

@ -267,11 +267,13 @@ _intel_batchbuffer_flush(struct intel_batchbuffer *batch, const char *file,
GLboolean
intel_batchbuffer_emit_reloc(struct intel_batchbuffer *batch,
dri_bo *buffer,
GLuint flags, GLuint delta)
uint32_t read_domains, uint32_t write_domain,
uint32_t delta)
{
int ret;
ret = dri_emit_reloc(batch->buf, flags, delta, batch->ptr - batch->map, buffer);
ret = dri_emit_reloc(batch->buf, read_domains, write_domain,
delta, batch->ptr - batch->map, buffer);
/*
* Using the old buffer offset, write in what the right data would be, in case

9
src/mesa/drivers/dri/intel/intel_batchbuffer.h
View file

@ -79,7 +79,9 @@ void intel_batchbuffer_release_space(struct intel_batchbuffer *batch,
GLboolean intel_batchbuffer_emit_reloc(struct intel_batchbuffer *batch,
dri_bo *buffer,
GLuint flags, GLuint offset);
uint32_t read_domains,
uint32_t write_domain,
uint32_t offset);
/* Inline functions - might actually be better off with these
* non-inlined. Certainly better off switching all command packets to
@ -131,9 +133,10 @@ intel_batchbuffer_require_space(struct intel_batchbuffer *batch,
#define OUT_BATCH(d) intel_batchbuffer_emit_dword(intel->batch, d)
#define OUT_RELOC(buf, cliprect_mode, delta) do { \
#define OUT_RELOC(buf, read_domains, write_domain, delta) do { \
assert((delta) >= 0); \
intel_batchbuffer_emit_reloc(intel->batch, buf, cliprect_mode, delta); \
intel_batchbuffer_emit_reloc(intel->batch, buf, \
read_domains, write_domain, delta); \
} while (0)
#define ADVANCE_BATCH() do { } while(0)

31
src/mesa/drivers/dri/intel/intel_blit.c
View file

@ -148,10 +148,14 @@ intelCopyBuffer(const __DRIdrawablePrivate * dPriv,
OUT_BATCH((box.y1 << 16) | box.x1);
OUT_BATCH((box.y2 << 16) | box.x2);
OUT_RELOC(dst->buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE, 0);
OUT_RELOC(dst->buffer,
DRM_GEM_DOMAIN_I915_RENDER, DRM_GEM_DOMAIN_I915_RENDER,
0);
OUT_BATCH((src_y << 16) | src_x);
OUT_BATCH(src_pitch);
OUT_RELOC(src->buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, 0);
OUT_RELOC(src->buffer,
DRM_GEM_DOMAIN_I915_RENDER, 0,
0);
ADVANCE_BATCH();
}
@ -212,7 +216,9 @@ intelEmitFillBlit(struct intel_context *intel,
OUT_BATCH(BR13 | dst_pitch);
OUT_BATCH((y << 16) | x);
OUT_BATCH(((y + h) << 16) | (x + w));
OUT_RELOC(dst_buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE, dst_offset);
OUT_RELOC(dst_buffer,
DRM_GEM_DOMAIN_I915_RENDER, DRM_GEM_DOMAIN_I915_RENDER,
dst_offset);
OUT_BATCH(color);
ADVANCE_BATCH();
}
@ -332,11 +338,13 @@ intelEmitCopyBlit(struct intel_context *intel,
OUT_BATCH(BR13 | dst_pitch);
OUT_BATCH((dst_y << 16) | dst_x);
OUT_BATCH((dst_y2 << 16) | dst_x2);
OUT_RELOC(dst_buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
OUT_RELOC(dst_buffer,
DRM_GEM_DOMAIN_I915_RENDER, DRM_GEM_DOMAIN_I915_RENDER,
dst_offset);
OUT_BATCH((src_y << 16) | src_x);
OUT_BATCH(src_pitch);
OUT_RELOC(src_buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
OUT_RELOC(src_buffer,
DRM_GEM_DOMAIN_I915_RENDER, 0,
src_offset);
ADVANCE_BATCH();
}
@ -349,11 +357,13 @@ intelEmitCopyBlit(struct intel_context *intel,
OUT_BATCH(BR13 | dst_pitch);
OUT_BATCH((0 << 16) | dst_x);
OUT_BATCH((h << 16) | dst_x2);
OUT_RELOC(dst_buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
OUT_RELOC(dst_buffer,
DRM_GEM_DOMAIN_I915_RENDER, DRM_GEM_DOMAIN_I915_RENDER,
dst_offset + dst_y * dst_pitch);
OUT_BATCH((0 << 16) | src_x);
OUT_BATCH(src_pitch);
OUT_RELOC(src_buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
OUT_RELOC(src_buffer,
DRM_GEM_DOMAIN_I915_RENDER, 0,
src_offset + src_y * src_pitch);
ADVANCE_BATCH();
}
@ -528,7 +538,8 @@ intelClearWithBlit(GLcontext *ctx, GLbitfield mask)
OUT_BATCH(BR13);
OUT_BATCH((b.y1 << 16) | b.x1);
OUT_BATCH((b.y2 << 16) | b.x2);
OUT_RELOC(write_buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
OUT_RELOC(write_buffer,
DRM_GEM_DOMAIN_I915_RENDER, DRM_GEM_DOMAIN_I915_RENDER,
irb_region->draw_offset);
OUT_BATCH(clearVal);
ADVANCE_BATCH();
@ -600,7 +611,9 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel,
OUT_BATCH(br13);
OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
OUT_RELOC(dst_buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE, dst_offset);
OUT_RELOC(dst_buffer,
DRM_GEM_DOMAIN_I915_RENDER, DRM_GEM_DOMAIN_I915_RENDER,
dst_offset);
OUT_BATCH(0); /* bg */
OUT_BATCH(fg_color); /* fg */
OUT_BATCH(0); /* pattern base addr */

57
src/mesa/drivers/dri/common/dri_bufmgr_fake.c → src/mesa/drivers/dri/intel/intel_bufmgr_fake.c
View file

@ -35,7 +35,9 @@
*/
#include "mtypes.h"
#include "dri_bufmgr.h"
#include "intel_bufmgr_fake.h"
#include "drm.h"
#include "i915_drm.h"
#include "simple_list.h"
#include "mm.h"
@ -70,8 +72,10 @@ struct fake_buffer_reloc
GLuint last_target_offset;
/** Value added to target_buf's offset to get the relocation entry. */
GLuint delta;
/** Flags to validate the target buffer under. */
uint64_t validate_flags;
/** Cache domains the target buffer is read into. */
uint32_t read_domains;
/** Cache domain the target buffer will have dirty cachelines in. */
uint32_t write_domain;
};
struct block {
@ -153,13 +157,15 @@ typedef struct _dri_bo_fake {
* driver private flags.
*/
uint64_t flags;
/** Cache domains the target buffer is read into. */
uint32_t read_domains;
/** Cache domain the target buffer will have dirty cachelines in. */
uint32_t write_domain;
unsigned int alignment;
GLboolean is_static, validated;
unsigned int map_count;
/* Flags for the buffer to be validated with in command submission */
uint64_t validate_flags;
/** relocation list */
struct fake_buffer_reloc *relocs;
GLuint nr_relocs;
@ -814,7 +820,7 @@ dri_fake_kick_all(dri_bufmgr_fake *bufmgr_fake)
}
static int
dri_fake_bo_validate(dri_bo *bo, uint64_t flags)
dri_fake_bo_validate(dri_bo *bo)
{
dri_bufmgr_fake *bufmgr_fake;
dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
@ -911,8 +917,9 @@ dri_fake_destroy(dri_bufmgr *bufmgr)
}
static int
dri_fake_emit_reloc(dri_bo *reloc_buf, uint64_t flags, GLuint delta,
GLuint offset, dri_bo *target_buf)
dri_fake_emit_reloc(dri_bo *reloc_buf,
uint32_t read_domains, uint32_t write_domain,
uint32_t delta, uint32_t offset, dri_bo *target_buf)
{
dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)reloc_buf->bufmgr;
struct fake_buffer_reloc *r;
@ -940,7 +947,8 @@ dri_fake_emit_reloc(dri_bo *reloc_buf, uint64_t flags, GLuint delta,
r->offset = offset;
r->last_target_offset = target_buf->offset;
r->delta = delta;
r->validate_flags = flags;
r->read_domains = read_domains;
r->write_domain = write_domain;
if (bufmgr_fake->debug) {
/* Check that a conflicting relocation hasn't already been emitted. */
@ -959,7 +967,7 @@ dri_fake_emit_reloc(dri_bo *reloc_buf, uint64_t flags, GLuint delta,
* the combined validation flags for the buffer on this batchbuffer submission.
*/
static void
dri_fake_calculate_validate_flags(dri_bo *bo)
dri_fake_calculate_domains(dri_bo *bo)
{
dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
int i;
@ -969,21 +977,11 @@ dri_fake_calculate_validate_flags(dri_bo *bo)
dri_bo_fake *target_fake = (dri_bo_fake *)r->target_buf;
/* Do the same for the tree of buffers we depend on */
dri_fake_calculate_validate_flags(r->target_buf);
dri_fake_calculate_domains(r->target_buf);
if (target_fake->validate_flags == 0) {
target_fake->validate_flags = r->validate_flags;
} else {
/* Mask the memory location to the intersection of all the memory
* locations the buffer is being validated to.
*/
target_fake->validate_flags =
(target_fake->validate_flags & ~DRM_BO_MASK_MEM) |
(r->validate_flags & target_fake->validate_flags &
DRM_BO_MASK_MEM);
/* All the other flags just accumulate. */
target_fake->validate_flags |= r->validate_flags & ~DRM_BO_MASK_MEM;
}
target_fake->read_domains |= r->read_domains;
if (target_fake->write_domain != 0)
target_fake->write_domain = r->write_domain;
}
}
@ -1028,7 +1026,7 @@ dri_fake_reloc_and_validate_buffer(dri_bo *bo)
if (bo->virtual != NULL)
dri_bo_unmap(bo);
if (bo_fake->validate_flags & DRM_BO_FLAG_WRITE) {
if (bo_fake->write_domain != 0) {
if (!(bo_fake->flags & (BM_NO_BACKING_STORE|BM_PINNED))) {
if (bo_fake->backing_store == 0)
alloc_backing_store(bo);
@ -1038,7 +1036,7 @@ dri_fake_reloc_and_validate_buffer(dri_bo *bo)
bufmgr_fake->performed_rendering = GL_TRUE;
}
return dri_fake_bo_validate(bo, bo_fake->validate_flags);
return dri_fake_bo_validate(bo);
}
static void *
@ -1051,9 +1049,9 @@ dri_fake_process_relocs(dri_bo *batch_buf)
bufmgr_fake->performed_rendering = GL_FALSE;
dri_fake_calculate_validate_flags(batch_buf);
dri_fake_calculate_domains(batch_buf);
batch_fake->validate_flags = DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ;
batch_fake->read_domains = DRM_GEM_DOMAIN_I915_COMMAND;
/* we've ran out of RAM so blow the whole lot away and retry */
restart:
@ -1095,7 +1093,8 @@ dri_bo_fake_post_submit(dri_bo *bo)
assert(bo_fake->map_count == 0);
bo_fake->validated = GL_FALSE;
bo_fake->validate_flags = 0;
bo_fake->read_domains = 0;
bo_fake->write_domain = 0;
}

50
src/mesa/drivers/dri/intel/intel_bufmgr_fake.h Normal file
View file

@ -0,0 +1,50 @@
/**************************************************************************
*
* Copyright © 2007 Intel Corporation
* Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
*
**************************************************************************/
/*
* Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
* Keith Whitwell <keithw-at-tungstengraphics-dot-com>
* Eric Anholt <eric@anholt.net>
*/
#ifndef _INTEL_BUFMGR_FAKE_H_
#define _INTEL_BUFMGR_FAKE_H_
void dri_bufmgr_fake_contended_lock_take(dri_bufmgr *bufmgr);
dri_bufmgr *dri_bufmgr_fake_init(unsigned long low_offset, void *low_virtual,
unsigned long size,
unsigned int (*fence_emit)(void *private),
int (*fence_wait)(void *private,
unsigned int cookie),
void *driver_priv);
void dri_bo_fake_disable_backing_store(dri_bo *bo,
void (*invalidate_cb)(dri_bo *bo,
void *ptr),
void *ptr);
#endif /* _INTEL_BUFMGR_FAKE_H_ */

30
src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
View file

@ -579,8 +579,8 @@ dri_bufmgr_gem_destroy(dri_bufmgr *bufmgr)
* last known offset in target_bo.
*/
static int
dri_gem_emit_reloc(dri_bo *bo, uint64_t flags, GLuint delta,
GLuint offset, dri_bo *target_bo)
dri_gem_emit_reloc(dri_bo *bo, uint32_t read_domains, uint32_t write_domain,
uint32_t delta, uint32_t offset, dri_bo *target_bo)
{
dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)bo->bufmgr;
dri_bo_gem *bo_gem = (dri_bo_gem *)bo;
@ -601,18 +601,17 @@ dri_gem_emit_reloc(dri_bo *bo, uint64_t flags, GLuint delta,
bo_gem->reloc_target_bo[bo_gem->reloc_count] = target_bo;
dri_bo_reference(target_bo);
/** XXX set memory domains, using existing TTM flags (which is wrong) */
if (flags & DRM_BO_FLAG_WRITE)
{
/* assume this means the rendering buffer */
target_bo_gem->read_domains |= DRM_GEM_DOMAIN_I915_RENDER;
target_bo_gem->write_domain = DRM_GEM_DOMAIN_I915_RENDER;
}
if (flags & DRM_BO_FLAG_READ)
{
/* assume this means the sampler buffer */
target_bo_gem->read_domains |= DRM_GEM_DOMAIN_I915_SAMPLER;
}
/* Just accumulate the read domains into the target buffer. We don't care
* enough about minimizing the flags associated with a buffer for a
* specific set of relocations being done against it.
*/
target_bo_gem->read_domains |= read_domains;
/* XXX: this is broken if we have more than one write domain. We
* would need to be computing the write domain on the buffer based on
* order of relocs in the batchbuffer. But we only have one write buffer.
*/
target_bo_gem->write_domain = write_domain;
bo_gem->reloc_count++;
return 0;
}
@ -699,9 +698,6 @@ dri_gem_post_submit(dri_bo *batch_buf)
dri_bo *bo = bufmgr_gem->validate_bo[i];
dri_bo_gem *bo_gem = (dri_bo_gem *)bo;
/* clear read/write domain bits */
bo_gem->read_domains = 0;
bo_gem->write_domain = 0;
/* Disconnect the buffer from the validate list */
bo_gem->validate_index = -1;
dri_bo_unreference(bo);

1
src/mesa/drivers/dri/intel/intel_context.c
View file

@ -59,6 +59,7 @@
#include "intel_buffer_objects.h"
#include "intel_fbo.h"
#include "intel_decode.h"
#include "intel_bufmgr_fake.h"
#include "intel_bufmgr_gem.h"
#include "drirenderbuffer.h"