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isl: Set tiling requirements for video surfaces

Browse source 
Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35927>
(cherry picked from commit 389ce946fd)
This commit is contained in:
Calder Young 2025-07-07 14:27:14 -07:00 • committed by Eric Engestrom
parent d8d6f3ef6f
commit eac79122c1
4 changed files with 34 additions and 1 deletions
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2
.pick_status.json
View file

@ -174,7 +174,7 @@
"description": "isl: Set tiling requirements for video surfaces",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": null,
"notes": null

12
src/intel/isl/isl_gfx12.c
View file

@ -135,6 +135,18 @@ isl_gfx125_filter_tiling(const struct isl_device *dev,
*/
if (info->usage & ISL_SURF_USAGE_CPB_BIT)
*flags &= ISL_TILING_4_BIT | ISL_TILING_64_BIT;
/* From ATS-M PRMs, Volume 2a: Command Reference: Instructions,
* MFX_SURFACE_STATE,
*
* "For optimizing memory efficiency based on access patterns, only
* TileY is supported."
*
* The other media engines have similar limitations, TileY is the only
* well-supported tiling mode that can easily be used on all of them.
*/
if (info->usage & ISL_SURF_USAGE_VIDEO_DECODE_BIT)
*flags &= ISL_TILING_4_BIT;
}
void

12
src/intel/isl/isl_gfx20.c
View file

@ -135,6 +135,18 @@ isl_gfx20_filter_tiling(const struct isl_device *dev,
*/
if (info->usage & ISL_SURF_USAGE_CPB_BIT)
*flags &= ISL_TILING_4_BIT | ISL_TILING_64_XE2_BIT;
/* From ATS-M PRMs, Volume 2a: Command Reference: Instructions,
* MFX_SURFACE_STATE,
*
* "For optimizing memory efficiency based on access patterns, only
* TileY is supported."
*
* The other media engines have similar limitations, TileY is the only
* well-supported tiling mode that can easily be used on all of them.
*/
if (info->usage & ISL_SURF_USAGE_VIDEO_DECODE_BIT)
*flags &= ISL_TILING_4_BIT;
}
void

9
src/intel/isl/isl_gfx7.c
View file

@ -363,6 +363,15 @@ isl_gfx6_filter_tiling(const struct isl_device *dev,
(dev->info->platform == INTEL_PLATFORM_SKL && dev->info->gt != 4))) {
*flags &= ISL_TILING_LINEAR_BIT;
}
/* From HSW PRMs, Volume 2b: Command Reference: Instructions,
* MFX_SURFACE_STATE,
*
* "For optimizing memory efficiency based on access patterns, only
* TileY is supported."
*/
if (info->usage & ISL_SURF_USAGE_VIDEO_DECODE_BIT)
*flags &= ISL_TILING_Y0_BIT;
}
void