diff --git a/.pick_status.json b/.pick_status.json
index 9fc288a4aec..a7c64857bea 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -174,7 +174,7 @@
         "description": "isl: Set tiling requirements for video surfaces",
         "nominated": true,
         "nomination_type": 1,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": null,
         "notes": null
diff --git a/src/intel/isl/isl_gfx12.c b/src/intel/isl/isl_gfx12.c
index 0b13dfad94a..c8724a136b6 100644
--- a/src/intel/isl/isl_gfx12.c
+++ b/src/intel/isl/isl_gfx12.c
@@ -135,6 +135,18 @@ isl_gfx125_filter_tiling(const struct isl_device *dev,
     */
    if (info->usage & ISL_SURF_USAGE_CPB_BIT)
       *flags &= ISL_TILING_4_BIT | ISL_TILING_64_BIT;
+
+   /* From ATS-M PRMs, Volume 2a: Command Reference: Instructions,
+    * MFX_SURFACE_STATE,
+    *
+    *    "For optimizing memory efficiency based on access patterns, only
+    *     TileY is supported."
+    *
+    * The other media engines have similar limitations, TileY is the only
+    * well-supported tiling mode that can easily be used on all of them.
+    */
+   if (info->usage & ISL_SURF_USAGE_VIDEO_DECODE_BIT)
+      *flags &= ISL_TILING_4_BIT;
 }
 
 void
diff --git a/src/intel/isl/isl_gfx20.c b/src/intel/isl/isl_gfx20.c
index 753b0864084..81955fa7269 100644
--- a/src/intel/isl/isl_gfx20.c
+++ b/src/intel/isl/isl_gfx20.c
@@ -135,6 +135,18 @@ isl_gfx20_filter_tiling(const struct isl_device *dev,
     */
    if (info->usage & ISL_SURF_USAGE_CPB_BIT)
       *flags &= ISL_TILING_4_BIT | ISL_TILING_64_XE2_BIT;
+
+   /* From ATS-M PRMs, Volume 2a: Command Reference: Instructions,
+    * MFX_SURFACE_STATE,
+    *
+    *    "For optimizing memory efficiency based on access patterns, only
+    *     TileY is supported."
+    *
+    * The other media engines have similar limitations, TileY is the only
+    * well-supported tiling mode that can easily be used on all of them.
+    */
+   if (info->usage & ISL_SURF_USAGE_VIDEO_DECODE_BIT)
+      *flags &= ISL_TILING_4_BIT;
 }
 
 void
diff --git a/src/intel/isl/isl_gfx7.c b/src/intel/isl/isl_gfx7.c
index 9c406b7306e..6dd8f1d1b4d 100644
--- a/src/intel/isl/isl_gfx7.c
+++ b/src/intel/isl/isl_gfx7.c
@@ -363,6 +363,15 @@ isl_gfx6_filter_tiling(const struct isl_device *dev,
         (dev->info->platform == INTEL_PLATFORM_SKL && dev->info->gt != 4))) {
           *flags &= ISL_TILING_LINEAR_BIT;
    }
+
+   /* From HSW PRMs, Volume 2b: Command Reference: Instructions,
+    * MFX_SURFACE_STATE,
+    *
+    *    "For optimizing memory efficiency based on access patterns, only
+    *     TileY is supported."
+    */
+   if (info->usage & ISL_SURF_USAGE_VIDEO_DECODE_BIT)
+      *flags &= ISL_TILING_Y0_BIT;
 }
 
 void