From e9c151fde65457b05a42c9cd997b9cbbeda0eae0 Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Fri, 9 Aug 2024 16:14:35 -0700 Subject: [PATCH] intel/brw: Make 16-bit ishl, ishr, and ushr SSA friendly No shader-db changes on any Intel platform. fossil-db: All Intel platforms had similar results. (Meteor Lake shown) Totals: Instrs: 152536266 -> 152535897 (-0.00%); split: -0.00%, +0.00% Cycle count: 17124901233 -> 17112329592 (-0.07%); split: -0.07%, +0.00% Spill count: 78571 -> 78525 (-0.06%) Fill count: 148178 -> 148132 (-0.03%) Totals from 210 (0.03% of 633223) affected shaders: Instrs: 514525 -> 514156 (-0.07%); split: -0.16%, +0.08% Cycle count: 4003540698 -> 3990969057 (-0.31%); split: -0.32%, +0.00% Spill count: 15632 -> 15586 (-0.29%) Fill count: 26241 -> 26195 (-0.18%) Reviewed-by: Kenneth Graunke Part-of: --- src/intel/compiler/brw_fs_nir.cpp | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 4e233a4ed20..0b609871d7e 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -1633,8 +1633,9 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, */ case nir_op_ishl: if (instr->def.bit_size < 32) { - bld.AND(result, op[1], brw_imm_ud(instr->def.bit_size - 1)); - bld.SHL(result, op[0], result); + bld.SHL(result, + op[0], + bld.AND(op[1], brw_imm_ud(instr->def.bit_size - 1))); } else { bld.SHL(result, op[0], op[1]); } @@ -1642,8 +1643,9 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, break; case nir_op_ishr: if (instr->def.bit_size < 32) { - bld.AND(result, op[1], brw_imm_ud(instr->def.bit_size - 1)); - bld.ASR(result, op[0], result); + bld.ASR(result, + op[0], + bld.AND(op[1], brw_imm_ud(instr->def.bit_size - 1))); } else { bld.ASR(result, op[0], op[1]); } @@ -1651,8 +1653,9 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, break; case nir_op_ushr: if (instr->def.bit_size < 32) { - bld.AND(result, op[1], brw_imm_ud(instr->def.bit_size - 1)); - bld.SHR(result, op[0], result); + bld.SHR(result, + op[0], + bld.AND(op[1], brw_imm_ud(instr->def.bit_size - 1))); } else { bld.SHR(result, op[0], op[1]); }