fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-01-07 21:40:20 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

radv: add support for VkMemoryBarrier2KHR

Browse source 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13549>
This commit is contained in:
Samuel Pitoiset 2021-10-12 17:54:41 +02:00 • committed by Marge Bot
parent 3da7d10d9b
commit e99c66ad19
1 changed files with 22 additions and 8 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

30
src/amd/vulkan/radv_pass.c
View file

@ -45,16 +45,30 @@ radv_render_pass_add_subpass_dep(struct radv_render_pass *pass, const VkSubpassD
if (src == VK_SUBPASS_EXTERNAL)
dst = 0;
/* From the Vulkan 1.2.195 spec:
*
* "If an instance of VkMemoryBarrier2 is included in the pNext chain, srcStageMask,
* dstStageMask, srcAccessMask, and dstAccessMask parameters are ignored. The synchronization
* and access scopes instead are defined by the parameters of VkMemoryBarrier2."
*/
const VkMemoryBarrier2KHR *barrier =
vk_find_struct_const(dep->pNext, MEMORY_BARRIER_2_KHR);
VkPipelineStageFlags2KHR src_stage_mask = barrier ? barrier->srcStageMask : dep->srcStageMask;
VkAccessFlags2KHR src_access_mask = barrier ? barrier->srcAccessMask : dep->srcAccessMask;
VkPipelineStageFlags2KHR dst_stage_mask = barrier ? barrier->dstStageMask : dep->dstStageMask;
VkAccessFlags2KHR dst_access_mask = barrier ? barrier->dstAccessMask : dep->dstAccessMask;
if (dst == VK_SUBPASS_EXTERNAL) {
if (dep->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
pass->end_barrier.src_stage_mask |= dep->srcStageMask;
pass->end_barrier.src_access_mask |= dep->srcAccessMask;
pass->end_barrier.dst_access_mask |= dep->dstAccessMask;
if (dst_stage_mask != VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT_KHR)
pass->end_barrier.src_stage_mask |= src_stage_mask;
pass->end_barrier.src_access_mask |= src_access_mask;
pass->end_barrier.dst_access_mask |= dst_access_mask;
} else {
if (dep->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
pass->subpasses[dst].start_barrier.src_stage_mask |= dep->srcStageMask;
pass->subpasses[dst].start_barrier.src_access_mask |= dep->srcAccessMask;
pass->subpasses[dst].start_barrier.dst_access_mask |= dep->dstAccessMask;
if (dst_stage_mask != VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT_KHR)
pass->subpasses[dst].start_barrier.src_stage_mask |= src_stage_mask;
pass->subpasses[dst].start_barrier.src_access_mask |= src_access_mask;
pass->subpasses[dst].start_barrier.dst_access_mask |= dst_access_mask;
}
}