From e99c66ad196b46c4ea13c153dfd8f6f9cb701a76 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Tue, 12 Oct 2021 17:54:41 +0200 Subject: [PATCH] radv: add support for VkMemoryBarrier2KHR Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen Part-of: --- src/amd/vulkan/radv_pass.c | 30 ++++++++++++++++++++++-------- 1 file changed, 22 insertions(+), 8 deletions(-) diff --git a/src/amd/vulkan/radv_pass.c b/src/amd/vulkan/radv_pass.c index 4935600b27f..591eb35b8bc 100644 --- a/src/amd/vulkan/radv_pass.c +++ b/src/amd/vulkan/radv_pass.c @@ -45,16 +45,30 @@ radv_render_pass_add_subpass_dep(struct radv_render_pass *pass, const VkSubpassD if (src == VK_SUBPASS_EXTERNAL) dst = 0; + + /* From the Vulkan 1.2.195 spec: + * + * "If an instance of VkMemoryBarrier2 is included in the pNext chain, srcStageMask, + * dstStageMask, srcAccessMask, and dstAccessMask parameters are ignored. The synchronization + * and access scopes instead are defined by the parameters of VkMemoryBarrier2." + */ + const VkMemoryBarrier2KHR *barrier = + vk_find_struct_const(dep->pNext, MEMORY_BARRIER_2_KHR); + VkPipelineStageFlags2KHR src_stage_mask = barrier ? barrier->srcStageMask : dep->srcStageMask; + VkAccessFlags2KHR src_access_mask = barrier ? barrier->srcAccessMask : dep->srcAccessMask; + VkPipelineStageFlags2KHR dst_stage_mask = barrier ? barrier->dstStageMask : dep->dstStageMask; + VkAccessFlags2KHR dst_access_mask = barrier ? barrier->dstAccessMask : dep->dstAccessMask; + if (dst == VK_SUBPASS_EXTERNAL) { - if (dep->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT) - pass->end_barrier.src_stage_mask |= dep->srcStageMask; - pass->end_barrier.src_access_mask |= dep->srcAccessMask; - pass->end_barrier.dst_access_mask |= dep->dstAccessMask; + if (dst_stage_mask != VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT_KHR) + pass->end_barrier.src_stage_mask |= src_stage_mask; + pass->end_barrier.src_access_mask |= src_access_mask; + pass->end_barrier.dst_access_mask |= dst_access_mask; } else { - if (dep->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT) - pass->subpasses[dst].start_barrier.src_stage_mask |= dep->srcStageMask; - pass->subpasses[dst].start_barrier.src_access_mask |= dep->srcAccessMask; - pass->subpasses[dst].start_barrier.dst_access_mask |= dep->dstAccessMask; + if (dst_stage_mask != VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT_KHR) + pass->subpasses[dst].start_barrier.src_stage_mask |= src_stage_mask; + pass->subpasses[dst].start_barrier.src_access_mask |= src_access_mask; + pass->subpasses[dst].start_barrier.dst_access_mask |= dst_access_mask; } }