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intel: Drop Tigerlake revision 0 workarounds

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Tigerlake revision 0 is an early stepping that should not be used in
production anywhere, so this code was only used for hardware bringup.
We can drop the unnecessary workarounds.  This also keeps them from
triggering on early steppings of other Gfx12 parts.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13266>
This commit is contained in:
Kenneth Graunke 2021-10-07 12:38:03 -07:00
parent 6ef192bddf
commit e79e1ca304
2 changed files with 3 additions and 35 deletions
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20
src/gallium/drivers/iris/iris_state.c
View file

@ -382,8 +382,6 @@ emit_state(struct iris_batch *batch,
static void static void
flush_before_state_base_change(struct iris_batch *batch) flush_before_state_base_change(struct iris_batch *batch)
{ {
const struct intel_device_info *devinfo = &batch->screen->devinfo;
/* Flush before emitting STATE_BASE_ADDRESS. /* Flush before emitting STATE_BASE_ADDRESS.
* *
* This isn't documented anywhere in the PRM. However, it seems to be * This isn't documented anywhere in the PRM. However, it seems to be
@ -409,18 +407,7 @@ flush_before_state_base_change(struct iris_batch *batch)
"change STATE_BASE_ADDRESS (flushes)", "change STATE_BASE_ADDRESS (flushes)",
PIPE_CONTROL_RENDER_TARGET_FLUSH | PIPE_CONTROL_RENDER_TARGET_FLUSH |
PIPE_CONTROL_DEPTH_CACHE_FLUSH | PIPE_CONTROL_DEPTH_CACHE_FLUSH |
PIPE_CONTROL_DATA_CACHE_FLUSH | PIPE_CONTROL_DATA_CACHE_FLUSH);
/* Wa_1606662791:
*
* Software must program PIPE_CONTROL command
* with "HDC Pipeline Flush" prior to
* programming of the below two non-pipeline
* state :
* * STATE_BASE_ADDRESS
* * 3DSTATE_BINDING_TABLE_POOL_ALLOC
*/
((GFX_VER == 12 && devinfo->revision == 0 /* A0 */ ?
PIPE_CONTROL_FLUSH_HDC : 0)));
} }
static void static void
@ -7560,8 +7547,7 @@ iris_emit_raw_pipe_control(struct iris_batch *batch,
imm); imm);
} }
if ((GFX_VER == 9 || (GFX_VER == 12 && devinfo->revision == 0 /* A0*/)) && if (GFX_VER == 9 && IS_COMPUTE_PIPELINE(batch) && post_sync_flags) {
IS_COMPUTE_PIPELINE(batch) && post_sync_flags) {
/* Project: SKL / Argument: LRI Post Sync Operation [23] /* Project: SKL / Argument: LRI Post Sync Operation [23]
* *
* "PIPECONTROL command with “Command Streamer Stall Enable” must be * "PIPECONTROL command with “Command Streamer Stall Enable” must be
@ -7570,8 +7556,6 @@ iris_emit_raw_pipe_control(struct iris_batch *batch,
* PIPELINE_SELECT command is set to GPGPU mode of operation)." * PIPELINE_SELECT command is set to GPGPU mode of operation)."
* *
* The same text exists a few rows below for Post Sync Op. * The same text exists a few rows below for Post Sync Op.
*
* On Gfx12 this is Wa_1607156449.
*/ */
iris_emit_raw_pipe_control(batch, iris_emit_raw_pipe_control(batch,
"workaround: CS stall before gpgpu post-sync", "workaround: CS stall before gpgpu post-sync",

18
src/intel/vulkan/genX_cmd_buffer.c
View file

@ -89,7 +89,6 @@ void
genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer) genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
{ {
struct anv_device *device = cmd_buffer->device; struct anv_device *device = cmd_buffer->device;
UNUSED const struct intel_device_info *devinfo = &device->info;
uint32_t mocs = isl_mocs(&device->isl_dev, 0, false); uint32_t mocs = isl_mocs(&device->isl_dev, 0, false);
/* If we are emitting a new state base address we probably need to re-emit /* If we are emitting a new state base address we probably need to re-emit
@ -112,17 +111,6 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
#endif #endif
pc.RenderTargetCacheFlushEnable = true; pc.RenderTargetCacheFlushEnable = true;
pc.CommandStreamerStallEnable = true; pc.CommandStreamerStallEnable = true;
#if GFX_VER == 12
/* Wa_1606662791:
*
* Software must program PIPE_CONTROL command with "HDC Pipeline
* Flush" prior to programming of the below two non-pipeline state :
* * STATE_BASE_ADDRESS
* * 3DSTATE_BINDING_TABLE_POOL_ALLOC
*/
if (devinfo->revision == 0 /* A0 */)
pc.HDCPipelineFlushEnable = true;
#endif
anv_debug_dump_pc(pc); anv_debug_dump_pc(pc);
} }
@ -2113,7 +2101,6 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer,
void void
genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer) genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer)
{ {
UNUSED const struct intel_device_info *devinfo = &cmd_buffer->device->info;
enum anv_pipe_bits bits = cmd_buffer->state.pending_pipe_bits; enum anv_pipe_bits bits = cmd_buffer->state.pending_pipe_bits;
if (unlikely(cmd_buffer->device->physical->always_flush_cache)) if (unlikely(cmd_buffer->device->physical->always_flush_cache))
@ -2196,12 +2183,9 @@ genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer)
* PIPELINE_SELECT command is set to GPGPU mode of operation)." * PIPELINE_SELECT command is set to GPGPU mode of operation)."
* *
* The same text exists a few rows below for Post Sync Op. * The same text exists a few rows below for Post Sync Op.
*
* On Gfx12 this is Wa_1607156449.
*/ */
if (bits & ANV_PIPE_POST_SYNC_BIT) { if (bits & ANV_PIPE_POST_SYNC_BIT) {
if ((GFX_VER == 9 || (GFX_VER == 12 && devinfo->revision == 0 /* A0 */)) && if (GFX_VER == 9 && cmd_buffer->state.current_pipeline == GPGPU)
cmd_buffer->state.current_pipeline == GPGPU)
bits |= ANV_PIPE_CS_STALL_BIT; bits |= ANV_PIPE_CS_STALL_BIT;
bits &= ~ANV_PIPE_POST_SYNC_BIT; bits &= ~ANV_PIPE_POST_SYNC_BIT;
} }