From e79e1ca304fd329a895c848048c784ce3f349d46 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Thu, 7 Oct 2021 12:38:03 -0700 Subject: [PATCH] intel: Drop Tigerlake revision 0 workarounds Tigerlake revision 0 is an early stepping that should not be used in production anywhere, so this code was only used for hardware bringup. We can drop the unnecessary workarounds. This also keeps them from triggering on early steppings of other Gfx12 parts. Reviewed-by: Francisco Jerez Part-of: --- src/gallium/drivers/iris/iris_state.c | 20 ++------------------ src/intel/vulkan/genX_cmd_buffer.c | 18 +----------------- 2 files changed, 3 insertions(+), 35 deletions(-) diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 901d76a768d..0cd8ce8ee97 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -382,8 +382,6 @@ emit_state(struct iris_batch *batch, static void flush_before_state_base_change(struct iris_batch *batch) { - const struct intel_device_info *devinfo = &batch->screen->devinfo; - /* Flush before emitting STATE_BASE_ADDRESS. * * This isn't documented anywhere in the PRM. However, it seems to be @@ -409,18 +407,7 @@ flush_before_state_base_change(struct iris_batch *batch) "change STATE_BASE_ADDRESS (flushes)", PIPE_CONTROL_RENDER_TARGET_FLUSH | PIPE_CONTROL_DEPTH_CACHE_FLUSH | - PIPE_CONTROL_DATA_CACHE_FLUSH | - /* Wa_1606662791: - * - * Software must program PIPE_CONTROL command - * with "HDC Pipeline Flush" prior to - * programming of the below two non-pipeline - * state : - * * STATE_BASE_ADDRESS - * * 3DSTATE_BINDING_TABLE_POOL_ALLOC - */ - ((GFX_VER == 12 && devinfo->revision == 0 /* A0 */ ? - PIPE_CONTROL_FLUSH_HDC : 0))); + PIPE_CONTROL_DATA_CACHE_FLUSH); } static void @@ -7560,8 +7547,7 @@ iris_emit_raw_pipe_control(struct iris_batch *batch, imm); } - if ((GFX_VER == 9 || (GFX_VER == 12 && devinfo->revision == 0 /* A0*/)) && - IS_COMPUTE_PIPELINE(batch) && post_sync_flags) { + if (GFX_VER == 9 && IS_COMPUTE_PIPELINE(batch) && post_sync_flags) { /* Project: SKL / Argument: LRI Post Sync Operation [23] * * "PIPECONTROL command with “Command Streamer Stall Enable” must be @@ -7570,8 +7556,6 @@ iris_emit_raw_pipe_control(struct iris_batch *batch, * PIPELINE_SELECT command is set to GPGPU mode of operation)." * * The same text exists a few rows below for Post Sync Op. - * - * On Gfx12 this is Wa_1607156449. */ iris_emit_raw_pipe_control(batch, "workaround: CS stall before gpgpu post-sync", diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index c884440e9ad..3079cd93fb3 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -89,7 +89,6 @@ void genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer) { struct anv_device *device = cmd_buffer->device; - UNUSED const struct intel_device_info *devinfo = &device->info; uint32_t mocs = isl_mocs(&device->isl_dev, 0, false); /* If we are emitting a new state base address we probably need to re-emit @@ -112,17 +111,6 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer) #endif pc.RenderTargetCacheFlushEnable = true; pc.CommandStreamerStallEnable = true; -#if GFX_VER == 12 - /* Wa_1606662791: - * - * Software must program PIPE_CONTROL command with "HDC Pipeline - * Flush" prior to programming of the below two non-pipeline state : - * * STATE_BASE_ADDRESS - * * 3DSTATE_BINDING_TABLE_POOL_ALLOC - */ - if (devinfo->revision == 0 /* A0 */) - pc.HDCPipelineFlushEnable = true; -#endif anv_debug_dump_pc(pc); } @@ -2113,7 +2101,6 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer, void genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer) { - UNUSED const struct intel_device_info *devinfo = &cmd_buffer->device->info; enum anv_pipe_bits bits = cmd_buffer->state.pending_pipe_bits; if (unlikely(cmd_buffer->device->physical->always_flush_cache)) @@ -2196,12 +2183,9 @@ genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer) * PIPELINE_SELECT command is set to GPGPU mode of operation)." * * The same text exists a few rows below for Post Sync Op. - * - * On Gfx12 this is Wa_1607156449. */ if (bits & ANV_PIPE_POST_SYNC_BIT) { - if ((GFX_VER == 9 || (GFX_VER == 12 && devinfo->revision == 0 /* A0 */)) && - cmd_buffer->state.current_pipeline == GPGPU) + if (GFX_VER == 9 && cmd_buffer->state.current_pipeline == GPGPU) bits |= ANV_PIPE_CS_STALL_BIT; bits &= ~ANV_PIPE_POST_SYNC_BIT; }