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ac,radeonsi: clear_state is not supported in user queue
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Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34370>
This commit is contained in:
Yogesh Mohan Marimuthu 2025-04-11 13:12:59 +05:30 • committed by Marge Bot
parent 61fd80a42e
commit e63b24bee8
2 changed files with 12 additions and 3 deletions
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3
src/amd/common/ac_gpu_info.c
View file

@ -1147,7 +1147,8 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
* on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
* SPI_VS_OUT_CONFIG. So only enable GFX7 CLEAR_STATE on amdgpu kernel.
*/
info->has_clear_state = info->gfx_level >= GFX7 && info->gfx_level < GFX12;
info->has_clear_state = info->gfx_level >= GFX7 && info->gfx_level < GFX12 &&
!(info->userq_ip_mask & BITFIELD_BIT(AMD_IP_GFX));
info->has_distributed_tess =
info->gfx_level >= GFX10 || (info->gfx_level >= GFX8 && info->max_se >= 2);

12
src/gallium/drivers/radeonsi/si_state.c
View file

@ -5123,8 +5123,16 @@ static void gfx10_init_gfx_preamble_state(struct si_context *sctx)
ac_pm4_cmd_add(&pm4->base, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
}
ac_pm4_cmd_add(&pm4->base, PKT3(PKT3_CLEAR_STATE, 0, 0));
ac_pm4_cmd_add(&pm4->base, 0);
if (sscreen->info.has_clear_state) {
ac_pm4_cmd_add(&pm4->base, PKT3(PKT3_CLEAR_STATE, 0, 0));
ac_pm4_cmd_add(&pm4->base, 0);
} else {
/* PA_SC_TILE_STEERING_OVERRIDE needs to be written else observing corruption in
* gfx11 with userq.
*/
ac_pm4_set_reg(&pm4->base, R_02835C_PA_SC_TILE_STEERING_OVERRIDE,
sscreen->info.pa_sc_tile_steering_override);
}
}
si_init_compute_preamble_state(sctx, pm4);