diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index d406c7ab29a..9f7619d5a39 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -1147,7 +1147,8 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
     * on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
     * SPI_VS_OUT_CONFIG. So only enable GFX7 CLEAR_STATE on amdgpu kernel.
     */
-   info->has_clear_state = info->gfx_level >= GFX7 && info->gfx_level < GFX12;
+   info->has_clear_state = info->gfx_level >= GFX7 && info->gfx_level < GFX12 &&
+                           !(info->userq_ip_mask & BITFIELD_BIT(AMD_IP_GFX));
 
    info->has_distributed_tess =
       info->gfx_level >= GFX10 || (info->gfx_level >= GFX8 && info->max_se >= 2);
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 8061be47aa7..81373d34300 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -5123,8 +5123,16 @@ static void gfx10_init_gfx_preamble_state(struct si_context *sctx)
          ac_pm4_cmd_add(&pm4->base, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
       }
 
-      ac_pm4_cmd_add(&pm4->base, PKT3(PKT3_CLEAR_STATE, 0, 0));
-      ac_pm4_cmd_add(&pm4->base, 0);
+      if (sscreen->info.has_clear_state) {
+         ac_pm4_cmd_add(&pm4->base, PKT3(PKT3_CLEAR_STATE, 0, 0));
+         ac_pm4_cmd_add(&pm4->base, 0);
+      } else {
+         /* PA_SC_TILE_STEERING_OVERRIDE needs to be written else observing corruption in
+          * gfx11 with userq.
+          */
+         ac_pm4_set_reg(&pm4->base, R_02835C_PA_SC_TILE_STEERING_OVERRIDE,
+                        sscreen->info.pa_sc_tile_steering_override);
+      }
    }
 
    si_init_compute_preamble_state(sctx, pm4);