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anv: fix buffer marker cache flush issues on MTL

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For some yet unknown reason the CS L3 coherency setting is different
on MTL than DG2.

Fixes issues in tests from the subgroup :

  dEQP-VK.api.buffer_marker.*

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: c8e122a738 ("anv: Implement rudimentary VK_AMD_buffer_marker support")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27613>
This commit is contained in:
Lionel Landwerlin 2024-02-13 10:39:05 +00:00 • committed by Marge Bot
parent 88d0c6c26a
commit e54638ddf5
2 changed files with 11 additions and 4 deletions
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9
src/intel/vulkan/anv_private.h
View file

@ -3072,6 +3072,15 @@ enum anv_query_bits {
ANV_QUERY_WRITES_DATA_FLUSH = (1 << 3),
};
/* It's not clear why DG2 doesn't have issues with L3/CS coherency. But it's
* likely related to performance workaround 14015868140.
*
* For now we enable this only on DG2 and platform prior to Gfx12 where there
* is no tile cache.
*/
#define ANV_DEVINFO_HAS_COHERENT_L3_CS(devinfo) \
(intel_device_info_is_dg2(devinfo))
/* Things we need to flush before accessing query data using the command
* streamer.
*

6
src/intel/vulkan/genX_cmd_buffer.c
View file

@ -5808,10 +5808,8 @@ genX(CmdWriteBufferMarker2AMD)(VkCommandBuffer commandBuffer,
* cache flushes.
*/
enum anv_pipe_bits bits =
#if GFX_VERx10 < 125
ANV_PIPE_DATA_CACHE_FLUSH_BIT |
ANV_PIPE_TILE_CACHE_FLUSH_BIT |
#endif
(ANV_DEVINFO_HAS_COHERENT_L3_CS(cmd_buffer->device->info) ? 0 :
(ANV_PIPE_DATA_CACHE_FLUSH_BIT | ANV_PIPE_TILE_CACHE_FLUSH_BIT)) |
ANV_PIPE_END_OF_PIPE_SYNC_BIT;
trace_intel_begin_write_buffer_marker(&cmd_buffer->trace);