diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 324dd8e7197..11e1b55e1e1 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -3072,6 +3072,15 @@ enum anv_query_bits {
    ANV_QUERY_WRITES_DATA_FLUSH    = (1 << 3),
 };
 
+/* It's not clear why DG2 doesn't have issues with L3/CS coherency. But it's
+ * likely related to performance workaround 14015868140.
+ *
+ * For now we enable this only on DG2 and platform prior to Gfx12 where there
+ * is no tile cache.
+ */
+#define ANV_DEVINFO_HAS_COHERENT_L3_CS(devinfo) \
+   (intel_device_info_is_dg2(devinfo))
+
 /* Things we need to flush before accessing query data using the command
  * streamer.
  *
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index 6c582147343..92f9252f7c5 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -5808,10 +5808,8 @@ genX(CmdWriteBufferMarker2AMD)(VkCommandBuffer commandBuffer,
     * cache flushes.
     */
    enum anv_pipe_bits bits =
-#if GFX_VERx10 < 125
-      ANV_PIPE_DATA_CACHE_FLUSH_BIT |
-      ANV_PIPE_TILE_CACHE_FLUSH_BIT |
-#endif
+      (ANV_DEVINFO_HAS_COHERENT_L3_CS(cmd_buffer->device->info) ? 0 :
+       (ANV_PIPE_DATA_CACHE_FLUSH_BIT | ANV_PIPE_TILE_CACHE_FLUSH_BIT)) |
       ANV_PIPE_END_OF_PIPE_SYNC_BIT;
 
    trace_intel_begin_write_buffer_marker(&cmd_buffer->trace);