fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-08 02:38:04 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

nir/ifind_msb_rev: fix input check

Browse source 
ifind_msb_rev was introduced in a5747f8ab3.

ifind_msb_rev guards against src0 being both 0 or -1 at the same time.
That is always true. This patch changes it to check for those values
individually.

Spotted from a compile warning.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

Fixes: a5747f8ab3 (\"nir: add opcodes for *find_msb_rev and lowering\")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11630>
(cherry picked from commit ffea622604)
This commit is contained in:
Thomas H.P. Andersen 2021-06-29 00:54:40 +02:00 • committed by Eric Engestrom
parent 965fb52f47
commit e41eb8950b
2 changed files with 2 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
.pick_status.json
View file

@ -4036,7 +4036,7 @@
"description": "nir/ifind_msb_rev: fix input check",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": "a5747f8ab357ff00c630b937b221e5fb59d90289"
},

2
src/compiler/nir/nir_opcodes.py
View file

@ -489,7 +489,7 @@ for (int bit = 31; bit >= 0; bit--) {
unop_convert("ifind_msb_rev", tint32, tuint, """
dst = -1;
if (src0 != 0 || src0 != -1) {
if (src0 != 0 && src0 != -1) {
for (int bit = 0; bit < 31; bit++) {
/* If src0 < 0, we're looking for the first 0 bit.
* if src0 >= 0, we're looking for the first 1 bit.