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radv: Add bool return value to radv_nir_lower_abi.

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And stop using it with the deprecated NIR_PASS_V macro.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33609>
This commit is contained in:
Timur Kristóf 2025-02-17 23:35:55 +01:00
parent 7147559156
commit e3e2ba4eb5
4 changed files with 11 additions and 5 deletions
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2
src/amd/vulkan/nir/radv_nir.h
View file

@ -29,7 +29,7 @@ struct radv_graphics_state_key;
void radv_nir_apply_pipeline_layout(nir_shader *shader, struct radv_device *device,
const struct radv_shader_stage *stage);
void radv_nir_lower_abi(nir_shader *shader, enum amd_gfx_level gfx_level, const struct radv_shader_stage *stage,
bool radv_nir_lower_abi(nir_shader *shader, enum amd_gfx_level gfx_level, const struct radv_shader_stage *stage,
const struct radv_graphics_state_key *gfx_state, uint32_t address32_hi);
bool radv_nir_lower_hit_attrib_derefs(nir_shader *shader);

10
src/amd/vulkan/nir/radv_nir_lower_abi.c
View file

@ -493,10 +493,12 @@ load_gsvs_ring(nir_builder *b, lower_abi_state *s, unsigned stream_id)
return nir_vector_insert_imm(b, ring, nir_imm_int(b, s->info->wave_size), 2);
}
void
bool
radv_nir_lower_abi(nir_shader *shader, enum amd_gfx_level gfx_level, const struct radv_shader_stage *stage,
const struct radv_graphics_state_key *gfx_state, uint32_t address32_hi)
{
bool progress = false;
lower_abi_state state = {
.gfx_level = gfx_level,
.info = &stage->info,
@ -512,7 +514,11 @@ radv_nir_lower_abi(nir_shader *shader, enum amd_gfx_level gfx_level, const struc
u_foreach_bit (i, shader->info.gs.active_stream_mask)
state.gsvs_ring[i] = load_gsvs_ring(&b, &state, i);
progress = true;
nir_metadata_preserve(impl, nir_metadata_control_flow);
}
nir_shader_intrinsics_pass(shader, lower_abi_instr, nir_metadata_control_flow, &state);
progress |= nir_shader_intrinsics_pass(shader, lower_abi_instr, nir_metadata_control_flow, &state);
return progress;
}

2
src/amd/vulkan/radv_pipeline.c
View file

@ -506,7 +506,7 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_graphics_stat
pdev->info.has_ls_vgpr_init_bug && gfx_state && !gfx_state->vs.has_prolog,
radv_select_hw_stage(&stage->info, gfx_level), stage->info.wave_size, stage->info.workgroup_size,
&stage->args.ac);
NIR_PASS_V(stage->nir, radv_nir_lower_abi, gfx_level, stage, gfx_state, pdev->info.address32_hi);
NIR_PASS(_, stage->nir, radv_nir_lower_abi, gfx_level, stage, gfx_state, pdev->info.address32_hi);
if (!stage->key.optimisations_disabled) {
NIR_PASS(_, stage->nir, nir_opt_dce);

2
src/amd/vulkan/radv_pipeline_graphics.c
View file

@ -2283,7 +2283,7 @@ radv_create_gs_copy_shader(struct radv_device *device, struct vk_pipeline_cache
NIR_PASS_V(nir, ac_nir_lower_intrinsics_to_args, pdev->info.gfx_level, pdev->info.has_ls_vgpr_init_bug,
AC_HW_VERTEX_SHADER, 64, 64, &gs_copy_stage.args.ac);
NIR_PASS_V(nir, radv_nir_lower_abi, pdev->info.gfx_level, &gs_copy_stage, gfx_state, pdev->info.address32_hi);
NIR_PASS(_, nir, radv_nir_lower_abi, pdev->info.gfx_level, &gs_copy_stage, gfx_state, pdev->info.address32_hi);
struct radv_graphics_pipeline_key key = {0};
bool dump_shader = radv_can_dump_shader(device, nir);