From e3e2ba4eb5a82f33949fcff496c92167e248b22d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Mon, 17 Feb 2025 23:35:55 +0100 Subject: [PATCH] radv: Add bool return value to radv_nir_lower_abi. And stop using it with the deprecated NIR_PASS_V macro. Reviewed-by: Alyssa Rosenzweig Part-of: --- src/amd/vulkan/nir/radv_nir.h | 2 +- src/amd/vulkan/nir/radv_nir_lower_abi.c | 10 ++++++++-- src/amd/vulkan/radv_pipeline.c | 2 +- src/amd/vulkan/radv_pipeline_graphics.c | 2 +- 4 files changed, 11 insertions(+), 5 deletions(-) diff --git a/src/amd/vulkan/nir/radv_nir.h b/src/amd/vulkan/nir/radv_nir.h index 462a1e761c0..68fbba360bf 100644 --- a/src/amd/vulkan/nir/radv_nir.h +++ b/src/amd/vulkan/nir/radv_nir.h @@ -29,7 +29,7 @@ struct radv_graphics_state_key; void radv_nir_apply_pipeline_layout(nir_shader *shader, struct radv_device *device, const struct radv_shader_stage *stage); -void radv_nir_lower_abi(nir_shader *shader, enum amd_gfx_level gfx_level, const struct radv_shader_stage *stage, +bool radv_nir_lower_abi(nir_shader *shader, enum amd_gfx_level gfx_level, const struct radv_shader_stage *stage, const struct radv_graphics_state_key *gfx_state, uint32_t address32_hi); bool radv_nir_lower_hit_attrib_derefs(nir_shader *shader); diff --git a/src/amd/vulkan/nir/radv_nir_lower_abi.c b/src/amd/vulkan/nir/radv_nir_lower_abi.c index a672d32bb96..041515c259e 100644 --- a/src/amd/vulkan/nir/radv_nir_lower_abi.c +++ b/src/amd/vulkan/nir/radv_nir_lower_abi.c @@ -493,10 +493,12 @@ load_gsvs_ring(nir_builder *b, lower_abi_state *s, unsigned stream_id) return nir_vector_insert_imm(b, ring, nir_imm_int(b, s->info->wave_size), 2); } -void +bool radv_nir_lower_abi(nir_shader *shader, enum amd_gfx_level gfx_level, const struct radv_shader_stage *stage, const struct radv_graphics_state_key *gfx_state, uint32_t address32_hi) { + bool progress = false; + lower_abi_state state = { .gfx_level = gfx_level, .info = &stage->info, @@ -512,7 +514,11 @@ radv_nir_lower_abi(nir_shader *shader, enum amd_gfx_level gfx_level, const struc u_foreach_bit (i, shader->info.gs.active_stream_mask) state.gsvs_ring[i] = load_gsvs_ring(&b, &state, i); + + progress = true; + nir_metadata_preserve(impl, nir_metadata_control_flow); } - nir_shader_intrinsics_pass(shader, lower_abi_instr, nir_metadata_control_flow, &state); + progress |= nir_shader_intrinsics_pass(shader, lower_abi_instr, nir_metadata_control_flow, &state); + return progress; } diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 62af54a7963..5a361245ac9 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -506,7 +506,7 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_graphics_stat pdev->info.has_ls_vgpr_init_bug && gfx_state && !gfx_state->vs.has_prolog, radv_select_hw_stage(&stage->info, gfx_level), stage->info.wave_size, stage->info.workgroup_size, &stage->args.ac); - NIR_PASS_V(stage->nir, radv_nir_lower_abi, gfx_level, stage, gfx_state, pdev->info.address32_hi); + NIR_PASS(_, stage->nir, radv_nir_lower_abi, gfx_level, stage, gfx_state, pdev->info.address32_hi); if (!stage->key.optimisations_disabled) { NIR_PASS(_, stage->nir, nir_opt_dce); diff --git a/src/amd/vulkan/radv_pipeline_graphics.c b/src/amd/vulkan/radv_pipeline_graphics.c index f21e68562ee..50518df99ec 100644 --- a/src/amd/vulkan/radv_pipeline_graphics.c +++ b/src/amd/vulkan/radv_pipeline_graphics.c @@ -2283,7 +2283,7 @@ radv_create_gs_copy_shader(struct radv_device *device, struct vk_pipeline_cache NIR_PASS_V(nir, ac_nir_lower_intrinsics_to_args, pdev->info.gfx_level, pdev->info.has_ls_vgpr_init_bug, AC_HW_VERTEX_SHADER, 64, 64, &gs_copy_stage.args.ac); - NIR_PASS_V(nir, radv_nir_lower_abi, pdev->info.gfx_level, &gs_copy_stage, gfx_state, pdev->info.address32_hi); + NIR_PASS(_, nir, radv_nir_lower_abi, pdev->info.gfx_level, &gs_copy_stage, gfx_state, pdev->info.address32_hi); struct radv_graphics_pipeline_key key = {0}; bool dump_shader = radv_can_dump_shader(device, nir);