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intel/brw: Don't mention gfx7 limitations in shuffle comments

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We don't support gfx7 here anymore, so we needn't consider it.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28458>
This commit is contained in:
Kenneth Graunke 2024-03-27 16:19:53 -07:00 • committed by Marge Bot
parent 1d9e2b761a
commit e3d12cf72f
1 changed files with 5 additions and 6 deletions
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11
src/intel/compiler/brw_fs_generator.cpp
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@ -432,12 +432,11 @@ fs_generator::generate_shuffle(fs_inst *inst,
src.type = dst.type = brw_reg_type_from_bit_size(type_sz(src.type) * 8,
BRW_REGISTER_TYPE_UD);
/* Because we're using the address register, we're limited to 8-wide
* execution on gfx7. On gfx8, we're limited to 16-wide by the address
* register file and 8-wide for 64-bit types. We could try and make this
* instruction splittable higher up in the compiler but that gets weird
* because it reads all of the channels regardless of execution size. It's
* easier just to split it here.
/* Because we're using the address register, we're limited to 16-wide
* by the address register file and 8-wide for 64-bit types. We could try
* and make this instruction splittable higher up in the compiler but that
* gets weird because it reads all of the channels regardless of execution
* size. It's easier just to split it here.
*/
const unsigned lower_width =
element_sz(src) > 4 || element_sz(dst) > 4 ? 8 :