From e3d12cf72f1e67aa0b3e0574edcf6c5ffd6cf4b8 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Wed, 27 Mar 2024 16:19:53 -0700 Subject: [PATCH] intel/brw: Don't mention gfx7 limitations in shuffle comments We don't support gfx7 here anymore, so we needn't consider it. Reviewed-by: Ian Romanick Part-of: --- src/intel/compiler/brw_fs_generator.cpp | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index 3f9554182b5..e5ccc18463f 100644 --- a/src/intel/compiler/brw_fs_generator.cpp +++ b/src/intel/compiler/brw_fs_generator.cpp @@ -432,12 +432,11 @@ fs_generator::generate_shuffle(fs_inst *inst, src.type = dst.type = brw_reg_type_from_bit_size(type_sz(src.type) * 8, BRW_REGISTER_TYPE_UD); - /* Because we're using the address register, we're limited to 8-wide - * execution on gfx7. On gfx8, we're limited to 16-wide by the address - * register file and 8-wide for 64-bit types. We could try and make this - * instruction splittable higher up in the compiler but that gets weird - * because it reads all of the channels regardless of execution size. It's - * easier just to split it here. + /* Because we're using the address register, we're limited to 16-wide + * by the address register file and 8-wide for 64-bit types. We could try + * and make this instruction splittable higher up in the compiler but that + * gets weird because it reads all of the channels regardless of execution + * size. It's easier just to split it here. */ const unsigned lower_width = element_sz(src) > 4 || element_sz(dst) > 4 ? 8 :