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gallium/radeon: remove r600_surface::level_info

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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák 2016-10-26 13:47:11 +02:00
parent bf4d102ea3
commit e3697b4be6
3 changed files with 6 additions and 7 deletions
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1
src/gallium/drivers/radeon/r600_pipe_common.h
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@ -306,7 +306,6 @@ struct r600_texture {
struct r600_surface { struct r600_surface {
struct pipe_surface base; struct pipe_surface base;
const struct radeon_surf_level *level_info;
bool color_initialized; bool color_initialized;
bool depth_initialized; bool depth_initialized;

2
src/gallium/drivers/radeon/r600_texture.c
View file

@ -1756,7 +1756,6 @@ struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
unsigned width, unsigned height) unsigned width, unsigned height)
{ {
struct r600_common_context *rctx = (struct r600_common_context*)pipe; struct r600_common_context *rctx = (struct r600_common_context*)pipe;
struct r600_texture *rtex = (struct r600_texture*)texture;
struct r600_surface *surface = CALLOC_STRUCT(r600_surface); struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
if (!surface) if (!surface)
@ -1772,7 +1771,6 @@ struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
surface->base.width = width; surface->base.width = width;
surface->base.height = height; surface->base.height = height;
surface->base.u = templ->u; surface->base.u = templ->u;
surface->level_info = &rtex->surface.level[templ->u.tex.level];
if (texture->target != PIPE_BUFFER) if (texture->target != PIPE_BUFFER)
vi_dcc_disable_if_incompatible_format(rctx, texture, vi_dcc_disable_if_incompatible_format(rctx, texture,

10
src/gallium/drivers/radeonsi/si_state.c
View file

@ -2438,6 +2438,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom
/* Colorbuffers. */ /* Colorbuffers. */
for (i = 0; i < nr_cbufs; i++) { for (i = 0; i < nr_cbufs; i++) {
const struct radeon_surf_level *level_info;
unsigned pitch_tile_max, slice_tile_max, tile_mode_index; unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
unsigned cb_color_base, cb_color_fmask, cb_color_attrib; unsigned cb_color_base, cb_color_fmask, cb_color_attrib;
unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice; unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
@ -2453,6 +2454,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom
} }
tex = (struct r600_texture *)cb->base.texture; tex = (struct r600_texture *)cb->base.texture;
level_info = &tex->surface.level[cb->base.u.tex.level];
radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
&tex->resource, RADEON_USAGE_READWRITE, &tex->resource, RADEON_USAGE_READWRITE,
tex->resource.b.b.nr_samples > 1 ? tex->resource.b.b.nr_samples > 1 ?
@ -2472,12 +2474,12 @@ static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom
RADEON_PRIO_DCC); RADEON_PRIO_DCC);
/* Compute mutable surface parameters. */ /* Compute mutable surface parameters. */
pitch_tile_max = cb->level_info->nblk_x / 8 - 1; pitch_tile_max = level_info->nblk_x / 8 - 1;
slice_tile_max = cb->level_info->nblk_x * slice_tile_max = level_info->nblk_x *
cb->level_info->nblk_y / 64 - 1; level_info->nblk_y / 64 - 1;
tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false); tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
cb_color_base = (tex->resource.gpu_address + cb->level_info->offset) >> 8; cb_color_base = (tex->resource.gpu_address + level_info->offset) >> 8;
cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max); cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
cb_color_slice = S_028C68_TILE_MAX(slice_tile_max); cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
cb_color_attrib = cb->cb_color_attrib | cb_color_attrib = cb->cb_color_attrib |