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brw: use newer NIR constructs
nir_shader_intrinsics_pass() & NIR_PASS() Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Ivan Briano <ivan.briano@intel.com> Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34109>
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1 changed files with 84 additions and 85 deletions
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@ -292,56 +292,52 @@ is_output(nir_intrinsic_instr *intrin)
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intrin->intrinsic == nir_intrinsic_store_per_view_output;
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}
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struct remap_patch_urb_offset_state {
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const struct intel_vue_map *vue_map;
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enum tess_primitive_mode tes_primitive_mode;
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};
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static bool
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remap_patch_urb_offsets(nir_block *block, nir_builder *b,
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const struct intel_vue_map *vue_map,
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enum tess_primitive_mode tes_primitive_mode)
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remap_patch_urb_offsets(nir_builder *b, nir_intrinsic_instr *intrin, void *data)
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{
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nir_foreach_instr_safe(instr, block) {
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if (instr->type != nir_instr_type_intrinsic)
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continue;
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struct remap_patch_urb_offset_state *state = data;
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nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
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if (!(b->shader->info.stage == MESA_SHADER_TESS_CTRL && is_output(intrin)) &&
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!(b->shader->info.stage == MESA_SHADER_TESS_EVAL && is_input(intrin)))
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return false;
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gl_shader_stage stage = b->shader->info.stage;
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if (remap_tess_levels(b, intrin, state->tes_primitive_mode))
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return false;
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if ((stage == MESA_SHADER_TESS_CTRL && is_output(intrin)) ||
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(stage == MESA_SHADER_TESS_EVAL && is_input(intrin))) {
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int vue_slot = state->vue_map->varying_to_slot[intrin->const_index[0]];
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assert(vue_slot != -1);
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intrin->const_index[0] = vue_slot;
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if (remap_tess_levels(b, intrin, tes_primitive_mode))
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continue;
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nir_src *vertex = nir_get_io_arrayed_index_src(intrin);
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if (vertex) {
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if (nir_src_is_const(*vertex)) {
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intrin->const_index[0] += nir_src_as_uint(*vertex) *
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state->vue_map->num_per_vertex_slots;
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} else {
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b->cursor = nir_before_instr(&intrin->instr);
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int vue_slot = vue_map->varying_to_slot[intrin->const_index[0]];
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assert(vue_slot != -1);
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intrin->const_index[0] = vue_slot;
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/* Multiply by the number of per-vertex slots. */
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nir_def *vertex_offset =
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nir_imul(b,
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vertex->ssa,
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nir_imm_int(b,
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state->vue_map->num_per_vertex_slots));
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nir_src *vertex = nir_get_io_arrayed_index_src(intrin);
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if (vertex) {
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if (nir_src_is_const(*vertex)) {
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intrin->const_index[0] += nir_src_as_uint(*vertex) *
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vue_map->num_per_vertex_slots;
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} else {
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b->cursor = nir_before_instr(&intrin->instr);
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/* Add it to the existing offset */
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nir_src *offset = nir_get_io_offset_src(intrin);
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nir_def *total_offset =
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nir_iadd(b, vertex_offset,
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offset->ssa);
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/* Multiply by the number of per-vertex slots. */
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nir_def *vertex_offset =
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nir_imul(b,
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vertex->ssa,
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nir_imm_int(b,
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vue_map->num_per_vertex_slots));
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/* Add it to the existing offset */
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nir_src *offset = nir_get_io_offset_src(intrin);
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nir_def *total_offset =
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nir_iadd(b, vertex_offset,
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offset->ssa);
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nir_src_rewrite(offset, total_offset);
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}
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}
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nir_src_rewrite(offset, total_offset);
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}
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}
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return true;
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}
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@ -406,13 +402,13 @@ brw_nir_lower_vs_inputs(nir_shader *nir)
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* loaded as one vec4 or dvec4 per element (or matrix column), depending on
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* whether it is a double-precision type or not.
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*/
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nir_lower_io(nir, nir_var_shader_in, type_size_vec4,
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nir_lower_io_lower_64bit_to_32_new);
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NIR_PASS(_, nir, nir_lower_io, nir_var_shader_in, type_size_vec4,
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nir_lower_io_lower_64bit_to_32_new);
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/* This pass needs actual constants */
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nir_opt_constant_folding(nir);
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NIR_PASS(_, nir, nir_opt_constant_folding);
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nir_io_add_const_offset_to_base(nir, nir_var_shader_in);
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NIR_PASS(_, nir, nir_io_add_const_offset_to_base, nir_var_shader_in);
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/* Update shader_info::dual_slot_inputs */
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nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
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@ -547,13 +543,13 @@ brw_nir_lower_vue_inputs(nir_shader *nir,
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var->data.driver_location = var->data.location;
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/* Inputs are stored in vec4 slots, so use type_size_vec4(). */
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nir_lower_io(nir, nir_var_shader_in, type_size_vec4,
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nir_lower_io_lower_64bit_to_32);
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NIR_PASS(_, nir, nir_lower_io, nir_var_shader_in, type_size_vec4,
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nir_lower_io_lower_64bit_to_32);
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/* This pass needs actual constants */
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nir_opt_constant_folding(nir);
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NIR_PASS(_, nir, nir_opt_constant_folding);
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nir_io_add_const_offset_to_base(nir, nir_var_shader_in);
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NIR_PASS(_, nir, nir_io_add_const_offset_to_base, nir_var_shader_in);
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nir_foreach_function_impl(impl, nir) {
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nir_foreach_block(block, impl) {
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@ -595,21 +591,20 @@ brw_nir_lower_tes_inputs(nir_shader *nir, const struct intel_vue_map *vue_map)
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nir_foreach_shader_in_variable(var, nir)
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var->data.driver_location = var->data.location;
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nir_lower_io(nir, nir_var_shader_in, type_size_vec4,
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nir_lower_io_lower_64bit_to_32);
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NIR_PASS(_, nir, nir_lower_io, nir_var_shader_in, type_size_vec4,
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nir_lower_io_lower_64bit_to_32);
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/* This pass needs actual constants */
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nir_opt_constant_folding(nir);
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NIR_PASS(_, nir, nir_opt_constant_folding);
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nir_io_add_const_offset_to_base(nir, nir_var_shader_in);
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NIR_PASS(_, nir, nir_io_add_const_offset_to_base, nir_var_shader_in);
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nir_foreach_function_impl(impl, nir) {
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nir_builder b = nir_builder_create(impl);
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nir_foreach_block(block, impl) {
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remap_patch_urb_offsets(block, &b, vue_map,
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nir->info.tess._primitive_mode);
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}
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}
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NIR_PASS(_, nir, nir_shader_intrinsics_pass, remap_patch_urb_offsets,
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nir_metadata_control_flow,
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&(struct remap_patch_urb_offset_state) {
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.vue_map = vue_map,
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.tes_primitive_mode = nir->info.tess._primitive_mode,
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});
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}
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static bool
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@ -686,29 +681,33 @@ brw_nir_lower_fs_inputs(nir_shader *nir,
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}
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}
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nir_lower_io(nir, nir_var_shader_in, type_size_vec4,
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nir_lower_io_lower_64bit_to_32 |
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nir_lower_io_use_interpolated_input_intrinsics);
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NIR_PASS(_, nir, nir_lower_io,
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nir_var_shader_in, type_size_vec4,
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nir_lower_io_lower_64bit_to_32 |
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nir_lower_io_use_interpolated_input_intrinsics);
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if (devinfo->ver >= 11)
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nir_lower_interpolation(nir, ~0);
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NIR_PASS(_, nir, nir_lower_interpolation, ~0);
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if (key->multisample_fbo == INTEL_NEVER) {
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nir_lower_single_sampled(nir);
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NIR_PASS(_, nir, nir_lower_single_sampled);
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} else if (key->persample_interp == INTEL_ALWAYS) {
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nir_shader_intrinsics_pass(nir, lower_barycentric_per_sample,
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nir_metadata_control_flow,
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NULL);
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NIR_PASS(_, nir, nir_shader_intrinsics_pass,
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lower_barycentric_per_sample,
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nir_metadata_control_flow,
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NULL);
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}
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if (devinfo->ver < 20)
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nir_shader_intrinsics_pass(nir, lower_barycentric_at_offset,
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nir_metadata_control_flow,
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NULL);
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if (devinfo->ver < 20) {
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NIR_PASS(_, nir, nir_shader_intrinsics_pass,
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lower_barycentric_at_offset,
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nir_metadata_control_flow,
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NULL);
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}
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/* This pass needs actual constants */
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nir_opt_constant_folding(nir);
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NIR_PASS(_, nir, nir_opt_constant_folding);
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nir_io_add_const_offset_to_base(nir, nir_var_shader_in);
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NIR_PASS(_, nir, nir_io_add_const_offset_to_base, nir_var_shader_in);
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}
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void
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@ -718,9 +717,9 @@ brw_nir_lower_vue_outputs(nir_shader *nir)
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var->data.driver_location = var->data.location;
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}
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nir_lower_io(nir, nir_var_shader_out, type_size_vec4,
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nir_lower_io_lower_64bit_to_32);
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brw_nir_lower_per_view_outputs(nir);
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NIR_PASS(_, nir, nir_lower_io, nir_var_shader_out, type_size_vec4,
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nir_lower_io_lower_64bit_to_32);
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NIR_PASS(_, nir, brw_nir_lower_per_view_outputs);
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}
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void
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@ -731,20 +730,20 @@ brw_nir_lower_tcs_outputs(nir_shader *nir, const struct intel_vue_map *vue_map,
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var->data.driver_location = var->data.location;
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}
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nir_lower_io(nir, nir_var_shader_out, type_size_vec4,
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nir_lower_io_lower_64bit_to_32);
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NIR_PASS(_, nir, nir_lower_io, nir_var_shader_out, type_size_vec4,
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nir_lower_io_lower_64bit_to_32);
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/* This pass needs actual constants */
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nir_opt_constant_folding(nir);
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NIR_PASS(_, nir, nir_opt_constant_folding);
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nir_io_add_const_offset_to_base(nir, nir_var_shader_out);
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NIR_PASS(_, nir, nir_io_add_const_offset_to_base, nir_var_shader_out);
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nir_foreach_function_impl(impl, nir) {
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nir_builder b = nir_builder_create(impl);
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nir_foreach_block(block, impl) {
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remap_patch_urb_offsets(block, &b, vue_map, tes_primitive_mode);
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}
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}
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NIR_PASS(_, nir, nir_shader_intrinsics_pass, remap_patch_urb_offsets,
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nir_metadata_control_flow,
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&(struct remap_patch_urb_offset_state) {
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.vue_map = vue_map,
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.tes_primitive_mode = tes_primitive_mode,
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});
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}
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void
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@ -756,7 +755,7 @@ brw_nir_lower_fs_outputs(nir_shader *nir)
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SET_FIELD(var->data.location, BRW_NIR_FRAG_OUTPUT_LOCATION);
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}
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nir_lower_io(nir, nir_var_shader_out, type_size_dvec4, 0);
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NIR_PASS(_, nir, nir_lower_io, nir_var_shader_out, type_size_dvec4, 0);
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}
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static bool
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